A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance

Bailey, Steven W.; Rigge, Paul; Han, Jaeduk; Lin, Richard J.; Chang, Eric Y.; Mao, Howard; Wang, Zhongkai; Markley, Chick; Izraelevitz, Adam; Wang, Angie; Narevsky, Nathan; Bae, Woorham; Shauck, Steve; Montano, Sergio; Norsworthy, Justin; Razzaque, Munir; Hau, Wen; Lentiro, Akalu; Doerflein, Matthew; Heckendorn, Darin; McGrath, Jim; DeSeta, Franco; Shoham, Ronen; Stellfox, Mike; Snowden, Mark; Cole, Joseph; Fuhrman, Daniel R.; Richards, Brian; Bachrach, Jonathan; Alon, Elad; Nikolić, Borivoje

doi:10.1109/jssc.2019.2924090

Cited by 14 publications

(3 citation statements)

References 14 publications

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“…The main advantage of the single-chip solution relies in the fact that, with the same system, it is possible to both drive and sample the analogue front-end, perform the detection tasks and communicate with the rest of the vehicle all with the same platform. Other noticeable implementations of single-chip radar processing systems that include hardware acceleration of computationally intensive tasks are presented in [81][82][83].…”

Section: Digital Hardware Architectures For On-vehicle Sensing Tasksmentioning

confidence: 99%

A Survey of Automotive Radar and Lidar Signal Processing and Architectures

Giuffrida,

Masera,

Martina

2023

Chips

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In recent years, the development of Advanced Driver-Assistance Systems (ADASs) is driving the need for more reliable and precise on-vehicle sensing. Radar and lidar are crucial in this framework, since they allow sensing of vehicle’s surroundings. In such a scenario, it is necessary to master these sensing systems, and knowing their similarities and differences is important. Due to ADAS’s intrinsic real-time performance requirements, it is almost mandatory to be aware of the processing algorithms required by radar and lidar to understand what can be optimized and what actions can be taken to approach the real-time requirement. This review aims to present state-of-the-art radar and lidar technology, mainly focusing on modulation schemes and imaging systems, highlighting their weaknesses and strengths. Then, an overview of the sensor data processing algorithms is provided, with some considerations on what type of algorithms can be accelerated in hardware, pointing to some implementations from the literature. In conclusion, the basic concepts of sensor fusion are presented, and a comparison between radar and lidar is performed.

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Section: Digital Hardware Architectures For On-vehicle Sensing Tasksmentioning

confidence: 99%

A Survey of Automotive Radar and Lidar Signal Processing and Architectures

Giuffrida,

Masera,

Martina

2023

Chips

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“…The reader sends a specific frequency of radio wave energy to the transponder, activating it to transmit its internal data. The reader then receives, interprets and forwards this data to the application program for processing [ 9 , 10 ]. Various standards govern different operating frequencies and data rates, with High Frequency (HF) (13.56 MHz) and Ultra High Frequency (UHF) (US: 902–928 MHz; China: 840–845 MHz and 920–925 MHz; Europe: 865–868 MHz) being the most common [ 11 ].…”

Section: Introductionmentioning

confidence: 99%

A Fully Integrated RFID Reader SoC

Hu,

Mei,

et al. 2023

Micromachines

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The traditional RFID reader module relies on a discrete original design. This design integrates a microcontroller, high-frequency RFID reader IC and other multiple chips onto a PCB board, leading to bottlenecks in cost, power consumption, stability and reliability. To align with the trend towards high integration, miniaturization and low power consumption in RFID reader, this paper introduces a fully integrated RFID Reader SoC. The SoC employs the open-source Cortex-M0 core to integrate the RF transceiver, analog circuits, baseband protocol processing, memory and interface circuits into one chip. It’s compatible with ISO/IEC 14443 A-type and B-type and ISO/IEC 15693 transmission protocols and rates. Manufactured using a 0.18 μm process, the chip is compatible with multiple standards. The optimized design of the digital baseband control circuit results in a chip area of only 11.95 mm2 offering clear advantages in both area and integration compared to similar work.

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“…Zhong et al [15] presented a RISC-V SoC based on Visible Light Communication (VLC) for mobile payment applications. Bailey et al [16] demonstrated a signal analysis SoC consisting of a general-purpose RISC-V core with vector extensions and a fixed-function signal-processing accelerator. Enrique et al [17] used open-source software to develop AI IoT applications on RISC-V SoC.…”

Section: Introductionmentioning

confidence: 99%

Intelligent Security Monitoring System Based on RISC-V SoC

Yuan

et al. 2021

Electronics

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With the development of the economy and society, the demand for social security and stability increases. However, traditional security systems rely too much on human resources and are affected by uncontrollable community security factors. An intelligent security monitoring system can overcome the limitations of traditional systems and save human resources, contributing to public security. To build this system, a RISC-V SoC is first designed in this paper and implemented on the Nexys-Video Artix-7 FPGA. Then, the Linux operating system is transplanted and successfully run. Meanwhile, the driver of related hardware devices is designed independently. After that, three OpenCV-based object detection models including YOLO (You Only Look Once), Haar (Haar-like features), and LBP (Local Binary Pattern) are compared, and the LBP model is chosen to design applications. Finally, the processing speed of 1.25 s per frame is realized to detect and track moving objects. To sum up, we build an intelligent security monitoring system with real-time detection, tracking, and identification functions through hardware and software collaborative design. This paper also proposes a video downsampling technique. Based on this technique, the BRAM resource usage on the hardware side is reduced by 50% and the amount of pixel data that needs to be processed on the software side is reduced by 75%. A video downsampling technology is also proposed in this paper to achieve better video display effects under limited hardware resources. It provides conditions for future function expansion and improves the models’ processing speed. Additionally, it reduces the run time of the application and improves the system performance.

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A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance

Cited by 14 publications

References 14 publications

A Survey of Automotive Radar and Lidar Signal Processing and Architectures

A Survey of Automotive Radar and Lidar Signal Processing and Architectures

A Fully Integrated RFID Reader SoC

Intelligent Security Monitoring System Based on RISC-V SoC

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