With the development of the economy and society, the demand for social security and stability increases. However, traditional security systems rely too much on human resources and are affected by uncontrollable community security factors. An intelligent security monitoring system can overcome the limitations of traditional systems and save human resources, contributing to public security. To build this system, a RISC-V SoC is first designed in this paper and implemented on the Nexys-Video Artix-7 FPGA. Then, the Linux operating system is transplanted and successfully run. Meanwhile, the driver of related hardware devices is designed independently. After that, three OpenCV-based object detection models including YOLO (You Only Look Once), Haar (Haar-like features), and LBP (Local Binary Pattern) are compared, and the LBP model is chosen to design applications. Finally, the processing speed of 1.25 s per frame is realized to detect and track moving objects. To sum up, we build an intelligent security monitoring system with real-time detection, tracking, and identification functions through hardware and software collaborative design. This paper also proposes a video downsampling technique. Based on this technique, the BRAM resource usage on the hardware side is reduced by 50% and the amount of pixel data that needs to be processed on the software side is reduced by 75%. A video downsampling technology is also proposed in this paper to achieve better video display effects under limited hardware resources. It provides conditions for future function expansion and improves the models’ processing speed. Additionally, it reduces the run time of the application and improves the system performance.
The characteristics and action mechanisms of intentional interference sources were analyzed. Then, a fast detection method of intentional co-channel interference was proposed based on such technologies as real-time spectrum analysis, digital phosphor display, and co-channel signal direction-finding. Next, two classical intentional interference scenarios were reproduced, and interference sources were detected fast through the proposed method.
Modern processors usually adopt pipeline structure and often load data from memory. At that point, the load-use hazard will inevitably occur, which usually stall the pipeline and reduce performance. This paper introduces and compares two schemes to solve load-use hazard. One is the traditional scheme that detect hazard between ID stage and EXE stage, which stalls the pipeline and insert bubbles between the two instructions. In the scheme we proposed, we add a simple bypass unit between EXE and MEM stage that disables the stall of load-use hazard caused by the traditional scheme, which can reduce the bubble between the two instructions. It's quite a considerable benefit in eliminating bubbles especially in the long pipeline or programs of plenty load instructions. The scheme was implemented in the open source RISC-V SoC generator Rocket-chip and synthesized in SMIC 130-nm technology. The results show that the performance of the latter scheme is increased by 6.9% in the Dhrystone benchmark with the reasonable cost of area and power.
In application fields such as face recognition and image recognition using deep learning, more convolution operations are required for the increasing amount of data. Therefore, the use of systolic array acceleration is becoming a key technology trend to accelerate the development of deep learning applications. In previous designs, most of the systolic array used single-buffer or double-buffer structures, but most of them did not compare the difference between the two in detail. This work designs and implements a three-level systolic array generator, which can be configured in single-buffer or double-buffer modes. We also program the generated systolic array accelerator on Nexys-Vedio FPGA to explore the performance and overhead of single-buffer and double-buffer structure modes. The results show that the throughput of the double-buffer structure is increased by nearly 3 × compared to the single-buffer structure while only brings an additional 28% power consumption and 25% area overhead under the SIMC 130nm technology. And compared with the previous work, the proposed systolic array generator reduces power consumption by 75% and area overhead by 34% with almost no loss in performance.
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