A Model for the Metastability Delay of Sequential Elements

Abstract

It is well known that every sequential element may become metastable when provided with marginal inputs, such as input transitions occurring too close or input voltage not reaching a de¯ned HI or LO level. In this case the sequential element requires extra time to decide which digital output level to¯nally present, which is perceived as an output delay. The amount of this delay depends on how close the element's state is to the balance point, at which the delay may, theoretically, become in¯nite. While metastability can be safely avoided within a closed timing domain, it cannot be completely ruled out at timing domain boundaries. Therefore it is important to quantify its e®ect. Traditionally this is done by means of a \mean time between upsets" (MTBU) which gives the expected interval between two metastable upsets. The latter is de¯ned as the event of latching the still undecided output of one sequential element by a subsequent one. However, such a de¯nition only makes sense in a time-safe environment like a synchronous design. In this paper we will extend the scope to so-called value-safe environments, in which a sequential element can safely¯nalize its decision, since the subsequent one waits for completion before capturing its output. Here metastability is not a matter of \failure" but a performance issue, and hence characterization by MTBU is not intuitive. Therefore we will put the focus on the delay aspect and derive a suitable model. This model extends existing approaches by also including the area of very weak metastability and thus providing complete coverage. We will show its validity through comparison with transistor-level simulation results for the most popular sequential elements in di®erent implementations, point out its relation to the traditional MTBU model parameters, namely and T 0 , and show how to use it for calculating the performance penalty in a value-safe environment.