A Modeling Framework for NBTI Degradation Under Dynamic Voltage and Frequency Scaling

Modeling of Static Negative Bias Temperature Stressing in p-channel VDMOSFETs using Least Square Method

“…NBT stress under static conditions results in notable threshold voltages shifts. These changes become more pronounced at higher stress voltages and temperatures, which is in line with other investigations [18,22,28,29]. A lot of results, including ours indicate that ∆V T saturates with increase in stress time [4,6,11].…”

Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories

“…The proposed model does not consider the exact sequence between active and drowsy modes, as in [31], [32]. Instead, the history of the memory operation over a long period of time is embedded in the parameter γ, which represents an average access ratio.…”

Negative bias temperature instability in SOI‐like p‐type metal oxide semiconductor devices

“…NBTI degradation mechanism has been debated in the past, and a large number of models have been proposed in the literature to explain various experimental signatures of NBTI (refer [16] for a detailed review of different models). However, it has been recently shown [17,18] that trap generation obtained from the double interface H-H 2 reaction-diffusion (RD) model, when augmented with the transient trap occupancy model as well as hole trapping in preexisting defects, can accurately predict measured stress and recovery data under wide range of experimental conditions. Therefore, in this Letter, the device characteristics are simulated in ATLAS [19][20][21] and the double interface H-H 2 RD model has been implemented for simulation of degradation during NBTI stress [22].…”