A Modified Empirical Mode Decomposition Filtering-Based Adaptive Phasor Estimation Algorithm for Removal of Exponentially Decaying DC Offset

Zhen, Jiang; Miao, Shihong; Liu, Pei

doi:10.1109/tpwrd.2014.2299808

Cited by 47 publications

(27 citation statements)

References 17 publications

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“…The MDF&DFT algorithm is used for the current and the DFT for the voltage. As above-mentioned, the objective is to take out the exponentially decaying DC offset [14], [17].…”

Section: Performance Of the Algorithmsmentioning

confidence: 99%

“…A method based on the DFT is proposed in [12], to estimate the decaying DC characteristic of the current signal and to compensate the effect of the decaying DC on the current phasor estimation based on stationary wavelet transform. Furthermore, this problem has been solved by mathematical modifications on the DFT filter [13] and by empirical mode decomposition [14], which allows removing a decaying DCoffset. Such strategies exhibit higher computational complexity than those based on the DFT, which cause increments in the phasor estimation time.…”

mentioning

confidence: 99%

“…The accomplished results indicate that the proposed algorithm is less sensitive to the exponential decaying DC, which may appear following any disturbance in an electrical power system. Likewise, it presents faster time response than the DFT and the empirical mode decomposition (EMD) [14] during transient conditions. The novelty of the paper may be summarized as follows.…”

mentioning

confidence: 99%

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An effective method for impedance estimation in distance relay based on DC offset removal

Vázquez

Ramı́rez

Zamora

et al. 2015

2015 IEEE Power &Amp; Energy Society General Meeting

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This paper proposes to combine the multipurpose digital filter (MDF) and the discrete Fourier transform (DFT) for the transmission lines impedance estimation under fault conditions. The digital filtering requirements in protecting relays are critical, because it is relevant to attain precise, fast, and reliable line impedance estimation from faulted current and voltage signals. In this paper, the proposed filter removes the exponentially decaying DC offset from the current signal, enhancing the impedance estimation under transient conditions, and reducing the time of estimation. Comparisons are made respect to the DFT with a one-cycle rectangular window. Simulations are carried out in order to assess the proposal.Index Terms--Digital filtering, exponential decaying, impedance estimation, phasor estimation, filtering, protective functions.I.

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“…The MDF&DFT algorithm is used for the current and the DFT for the voltage. As above-mentioned, the objective is to take out the exponentially decaying DC offset [14], [17].…”

Section: Performance Of the Algorithmsmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

See 1 more Smart Citation

An effective method for impedance estimation in distance relay based on DC offset removal

Vázquez

Ramı́rez

Zamora

et al. 2015

2015 IEEE Power &Amp; Energy Society General Meeting

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show abstract

“…In [19] the authors suggested the use of wavelet for phasor estimation, but as relays requires the phasor calculated based on the fundamental component of the signal and the estimated phasor may not be suitable for protection applications. The idea of using dynamic model of a signal to estimate phasor has been prominent in recent years [4], [13]. In [5], the dynamic phasor is modeled as complex polynomial.…”

Section: Introductionmentioning

confidence: 99%

“…TVE under different harmonic level HDPE or the proposed algorithm is utilized to estimate the phasor of a signal(13) corrupted in the presence of harmonics. The capability to estimate the phasor of a corrupted signal is shown inFig.…”

mentioning

confidence: 99%

Development of Phasor Estimation Algorithm for P-Class PMU Suitable in Protection Applications

Affijulla

Tripathy

2018

IEEE Trans. Smart Grid

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The paper proposes a phasor estimation algorithm for P-class PMU suitable in protection applications using Hilbert transform and convolution of a signal. As the protective relay requires extracted fundamental component of the phasor for its operation, the author's introduced an algorithm to estimate a robust phasor corresponding to the fundamental component which is close to the actual signal in L2-norm. Though IEEE C37.118.1a TM -2014 standard doesn't specify the accuracy requirements of phasor under transient condition, the performance of phasor estimator is tested under different dynamic conditions as per IEEE C37.118.1a TM -2014 standard. The effectiveness of proposed algorithm has also been verified on modified two area power system during fault along with the data generated by the experimental set-up in laboratory. The results revealed that the proposed algorithm estimates the phasor accurately irrespective of distortion present in the sinusoidal signals. Furthermore, the proposed estimator inherently filters harmonics, immune to decaying dc components, detects sharp changes in a signal during faults and effectively works under complex modulated conditions. The above scenario appears frequently in a power system with distributed energy sources. The simplicity, robustness and generality of the proposed algorithm suits for wide area measurement systems to measure the voltage and current phasors during disturbance in the smart power system networks.

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Field‐programmable gate array‐based design for real‐time computation of ensemble empirical mode decomposition

Das

Pradhan

2021

Circuit Theory & Apps

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Empirical mode decomposition (EMD) is considered as a suitable method when the signal to be analyzed is nonlinear or nonstationary in nature. But, EMD suffers from a problem known as mode mixing. To, reduce this problem, ensemble EMD (EEMD) was proposed. In this paper, we have presented a fast field-programmable gate array (FPGA)-based design for EEMD. Where calculation of output can be done in a parallel manner for different realizations.The design has a comparatively less execution time, and the execution time of the proposed EEMD design is even less than some state-of-the-art EMD-based design, although the architecture of EEMD is more complex, when compared with the EMD design. In this work, we have also performed an FPGA implementation of the EMD algorithm. The root mean square error (RMSE) and the correlation values of the intrinsic mode function (IMFs) obtained from the proposed EMD and EEMD designs are compared. The proposed FPGA-based architecture of the EEMD algorithm is designed using Verilog-hardware description language (HDL) and implemented on a Kintex-7 FPGA. The EEMD architecture consists of cubic Hermite spline interpolation (CHSI) and cubic spline interpolation (CSI) for the envelope generation. K E Y W O R D Sempirical mode decomposition (EMD), ensemble empirical mode decomposition (EEMD), field-programmable gate array (FPGA), parallel architectures

show abstract

A Modified Empirical Mode Decomposition Filtering-Based Adaptive Phasor Estimation Algorithm for Removal of Exponentially Decaying DC Offset

Cited by 47 publications

References 17 publications

An effective method for impedance estimation in distance relay based on DC offset removal

An effective method for impedance estimation in distance relay based on DC offset removal

Development of Phasor Estimation Algorithm for P-Class PMU Suitable in Protection Applications

Field‐programmable gate array‐based design for real‐time computation of ensemble empirical mode decomposition

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