A MOdular and Reprogrammable Real-time Processing Hardware, MORRPH

Drayer, Thomas H.; King, William E.; Tront, Joseph G.; Conners, Richard W.

doi:10.1109/fpga.1995.477404

Cited by 23 publications

(8 citation statements)

References 15 publications

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“…Thanks to the versatility to develop dedicated circuits and the high degree of parallelism, FPGAs can achieve performances similar to some other hardware alternatives that run at higher frequencies of operation. These reasons explain why the implementation of many algorithms is the focus of a wide number of works since the last decade, and why from early stages of the evolution of reconfigurable hardware, several FPGA-based custom computing machines have been designed to execute image processing or computer vision algorithms (Arnold et al, 1993;Drayer at al., 1995). Of high interest for AR applications is the implementation of object tracking algorithms, where different approaches have been followed.…”

Section: Fpga Applications In Image Processing and Computer Visionmentioning

confidence: 99%

Design of Embedded Augmented Reality Systems

Toledo¹,

Martínez²,

Garrigós³

et al. 2010

Augmented Reality

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Section: Fpga Applications In Image Processing and Computer Visionmentioning

confidence: 99%

Design of Embedded Augmented Reality Systems

Toledo¹,

Martínez²,

Garrigós³

et al. 2010

Augmented Reality

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“…In addition, they are often used as custom computing machines to solve compute-intensive problems [3,6,12,29]. A multi-FPGA system consists of several FPGA chips placed on a board and connected together through a routing structure.…”

Section: Introductionmentioning

confidence: 99%

Multi-terminal net routing for partial crossbar-based multi-FPGA systems

Ejnioui

Ranganathan

1999

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays

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Multi-FPGA systems are used as custom computing machines to solve compute intensive problems and also in the verification and prototyping of large circuits. In this paper, we address the problem of routing multi-terminal nets in a multi-FPGA system that uses partial crossbars as interconnect structures. First, we model the multi-terminal routing problem as a partitioned bin packing problem and formulate it as an integer linear programming problem where the number of variables is exponential. A fast heuristic is applied to compute an upper bound on the routing solution. Then, a column generation technique is used to solve the linear relaxation of the initial master problem in order to obtain a lower bound on the routing solution. This is followed by an iterative branch-and-price procedure that attempts to find a routing solution somewhere between the two established bounds. In this regard, the proposed algorithm guarantees an exact routing solution by searching a branch-and-price tree. Due to the tightness of the bounds, the branch-and-price tree is small resulting in shorter execution times. Experimental results are provided for different netlists and board configurations in order to demonstrate the algorithm's performance. The obtained results show that the algorithm finds an exact routing solution in a very short time.

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“…All FPGA-based reconfigurable systems can be broadly classified into two categories: systems with statically configured architectures [ 2 ] , [3], [4] and dynamically configurable architectures (run-time) [SI, [6]. The first type of reconfigurable systems can achieve very high performance.…”

Section: Introductionmentioning

confidence: 99%

Optimization of parallel task execution on the adaptive reconfigurable group organized computing system

Kirischian

Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000

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This paper presents the architecture organization of a task adaptive reconfigurable high-performance computing system for parallel processing of data--ow tasks. The architecture of this reconfigurable system allows flexible distribution of uniform configurable resources (FPGA-based) between tasks. Each task corresponds to a specific Group Processor (GP) adapted for the task requirements. The paper discusses the method of selecting the optimal group processor configuration and mapping group processors on the ,field of configurable resources. The performance results of the first prototype of the ARGO-parallel computing system are presented.

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A MOdular and Reprogrammable Real-time Processing Hardware, MORRPH

Cited by 23 publications

References 15 publications

Design of Embedded Augmented Reality Systems

Design of Embedded Augmented Reality Systems

Multi-terminal net routing for partial crossbar-based multi-FPGA systems

Optimization of parallel task execution on the adaptive reconfigurable group organized computing system

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