Multi-terminal net routing for partial crossbar-based multi-FPGA systems

Abstract

Multi-FPGA systems are used as custom computing machines to solve compute intensive problems and also in the verification and prototyping of large circuits. In this paper, we address the problem of routing multi-terminal nets in a multi-FPGA system that uses partial crossbars as interconnect structures. First, we model the multi-terminal routing problem as a partitioned bin packing problem and formulate it as an integer linear programming problem where the number of variables is exponential. A fast heuristic is applied to compute an upper bound on the routing solution. Then, a column generation technique is used to solve the linear relaxation of the initial master problem in order to obtain a lower bound on the routing solution. This is followed by an iterative branch-and-price procedure that attempts to find a routing solution somewhere between the two established bounds. In this regard, the proposed algorithm guarantees an exact routing solution by searching a branch-and-price tree. Due to the tightness of the bounds, the branch-and-price tree is small resulting in shorter execution times. Experimental results are provided for different netlists and board configurations in order to demonstrate the algorithm's performance. The obtained results show that the algorithm finds an exact routing solution in a very short time.

Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks

“…The approach presented in this paper complements the local interconnect resources in a 2D mesh-based CGRA with global interconnect resources based on multistage interconnection networks. During the 90's, multistage interconnection networks have been proposed in the context of system emulation platforms consisting of multiple FPGAs [45][46][47]. In those approaches, one or more FPGAs were used as interconnection devices.…”

“…In those approaches, one or more FPGAs were used as interconnection devices. They used for interconnection networks: Clos networks [45], Folded-Clos [46], and partial cross-bars [47].…”

Probabilistic optimization for FPGA board level routing problems

“…Given a BLRP instance, we determine a function such that in each chip there are no more than nets assigned to the same pin subset [4]. If we view each subset type as a bin, each net as an object, then the BLRP can be considered as a partitioned bin-packing problem [7].…”

Board-level multiterminal net assignment

“…Therefore, it is preferable to take the former approach. In [23], the multiterminal routing problem was formulated as an integer-linear programming problem where the number of variables and runtime are both exponential.…”

“…The problem was also referred to as the "partial crossbar interconnection structure" in [3]. The problem was studied using different approaches [8,9,10,13,23], where no experimental results for large problems were reported. Our satisfiability-based approach transforms the FPGA routing task into a single, large Boolean equation with the property that any assignment of input variables that satisfies the equation specifies a valid routing.…”