Board-level multiterminal net assignment

Song, Xiaoyu; Hung, William N. N.; Mishchenko, Alan; Chrzanowska-Jeske, M.; Coppola, A.; Kennings, Andrew

doi:10.1145/505306.505335

Cited by 3 publications

(3 citation statements)

References 18 publications

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“…pdx.edu/~whung/BLRP/. These are board-level multi-terminal net routing problems, arising in FPGA-based hardware design [26]. Actually, these problem instances were too hard for the solver to nish in acceptable time.…”

Section: Boolean Satis Abilitymentioning

confidence: 99%

Predicting algorithmic complexity through structure analysis and compression

Mann

Papp

2013

Applied Soft Computing

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The complexity of an algorithm is usually speci ed by the maximum number of steps made by the algorithm, as a function of the size of the input. However, as di erent inputs of equal size can yield dramatically di erent algorithm runtime, the size of the input is not always an appropriate basis for predicting algorithm runtime. In this paper, we argue that the compressed size of the input is more appropriate for this purpose. In particular, we devise a genetic algorithm for compressing a graph by nding the most compact description of its structure, and we demonstrate how the compressed size of the problem instance correlates with the runtime of an exact algorithm for two hard combinatorial problems (graph coloring and Boolean satis ability).

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Section: Boolean Satis Abilitymentioning

confidence: 99%

Predicting algorithmic complexity through structure analysis and compression

Mann

Papp

2013

Applied Soft Computing

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“…, for all (9) A generalized routing that uses at most l different tracks for routing any net is essentially the conjunction of formulae (5), (6), (7) and (9).…”

Section: Track Limitationsmentioning

confidence: 99%

“…We extend his method to the segmented channel routing. Although some work for FPGA routing via satisfiability has been done [2,5,9], but they are designed for the detailed routing, none of them consider the routability inside a segmented channel [3]. We formulate the case analysis for segmented channel routing.…”

Section: Introductionmentioning

confidence: 99%

On segmented channel routability

Hung

Song²,

Coppola³

et al.

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)

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We address the problem of checking the routability of segmented channels using satisfiability. The segmented channel routing problem arises in the context of row-based field programmable gate array (FPGAs). Our approach transforms the routing task into a single large Boolean equation such that any assignment of input variables that satisfies the equation specifies a valid routing. It considers all nets simultaneously and the absence of a satisfying assignment implies that the channel is unroutable. Empirical results show that the method is time-efficient and applicable to large problem instances.

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