A modular approach for reliable nanoelectronic and very-deep submicron circuit design based on analog neural network principles

Schmid, Alexandre; Leblebici, Yusuf

doi:10.1109/nano.2003.1230995

Cited by 14 publications

(9 citation statements)

References 13 publications

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“…Redundancy can be used at many different levels: at the device level (Tatapudi and Beiu, 2003;Schmid and Leblebici, 2003a), at the gate level (Schmid and Leblebici, 2003b), at the block level (Koushanfar et al, 2002), in time and in communication (through encoding (KleinOsowski and Lilja)), etc. Certainly the size of the device, gate, block or circuit increases in case of hardware and information redundancies.…”

Section: Errors Versus Techniquesmentioning

confidence: 99%

“…The new design technique improved the immunity to permanent and transient faults occurring at the transistor level. Another approach proposes a robust design of Boolean gates, specifically designed to absorb errors (Schmid and Leblebici, 2003b). Such gates could be incorporated in a library of fault tolerant gates, thus becoming transparent to the VLSI designers.…”

Section: Errors Versus Techniquesmentioning

confidence: 99%

See 1 more Smart Citation

A survey of memory error correcting techniques for improved reliability

Mukati

2011

Journal of Network and Computer Applications

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Section: Errors Versus Techniquesmentioning

confidence: 99%

Section: Errors Versus Techniquesmentioning

confidence: 99%

A survey of memory error correcting techniques for improved reliability

Mukati

2011

Journal of Network and Computer Applications

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“…Currently, common solutions assume knowledge of the underlying architecture and rely on reconfiguration and redundancy to achieve programming and fault tolerance [4], [5]. There have been two recent proposals on how to use such devices without knowledge of the underlying system [6], [7].…”

Section: Introductionmentioning

confidence: 99%

A model for variation- and fault-tolerant digital logic using self-assembled nanowire architectures

Goudarzi

Lakin

Stefanović

et al. 2014

Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures

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Abstract-Reconfiguration has been used for both defect-and fault-tolerant nanoscale architectures with regular structure. Recent advances in self-assembled nanowires have opened doors to a new class of electronic devices with irregular structure. For such devices, reservoir computing has been shown to be a viable approach to implement computation. This approach exploits the dynamical properties of a system rather than specifics of its structure. Here, we extend a model of reservoir computing, called the echo state network, to reflect more realistic aspects of self-assembled nanowire networks. As a proof of concept, we use echo state networks to implement basic building blocks of digital computing: AND, OR, and XOR gates, and 2-bit adder and multiplier circuits. We show that the system can operate perfectly in the presence of variations five orders of magnitude higher than ITRS's 2005 target, 6%, and achieves success rates 6 times higher than related approaches at half the cost. We also describe an adaptive algorithm that can detect faults in the system and reconfigure it to resume perfect operational condition.

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“…A fault-tolerant technique based on a four-layer architecture (named after layers naming conventions in artificial neural networks (ANNs) presented in [22] and [23]) is presented in Section II. The novel fault-tolerance analysis method is presented in Section III.…”

Section: Introductionmentioning

confidence: 99%

Optimization of the Averaging Reliability Technique Using Low Redundancy Factors for Nanoscale Technologies

Stanisavljević

Schmid

Leblebici

2009

IEEE Trans. Nanotechnology

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This paper presents a method enabling the evaluation of the averaging fault-tolerant technique, using the output probability density functions of unreliable units that are acquired from Monte Carlo simulations. The method has been verified by comparing numerical simulations and analytical developments. A faulttolerant four-layer architecture using averaging and with both fixed and adaptable threshold is compared with triple and R-fold modular redundancy (RMR) techniques, at gate level and using fault-free decision gates, showing that the redundancy factor can be reduced by a factor of two to three using the proposed four-layer architecture, in replacement of RMR, thus enabling significant savings in the area, and power dissipation. The analysis of the reliability of averaging techniques together with the redundancy optimization has been performed for the first time in the context of a large-scale system, showing that a target reliability can be achieved with low redundancy factors (R < 8) for moderate defect densities (device failure rate up to 10 −5 ). The performed analysis of the optimal size of the reliable islands (clusters) supports the assumption that clustering needs to be applied at the lower levels of design abstraction hierarchy, especially for fabrication technologies with increased defect density.Index Terms-Fault-tolerant architecture, high defect density, redundancy, reliability of nanoelectronic systems.1536-125X/$25.00

show abstract

A modular approach for reliable nanoelectronic and very-deep submicron circuit design based on analog neural network principles

Cited by 14 publications

References 13 publications

A survey of memory error correcting techniques for improved reliability

A survey of memory error correcting techniques for improved reliability

A model for variation- and fault-tolerant digital logic using self-assembled nanowire architectures

Optimization of the Averaging Reliability Technique Using Low Redundancy Factors for Nanoscale Technologies

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