Optimization of the Averaging Reliability Technique Using Low Redundancy Factors for Nanoscale Technologies

Abstract

This paper presents a method enabling the evaluation of the averaging fault-tolerant technique, using the output probability density functions of unreliable units that are acquired from Monte Carlo simulations. The method has been verified by comparing numerical simulations and analytical developments. A faulttolerant four-layer architecture using averaging and with both fixed and adaptable threshold is compared with triple and R-fold modular redundancy (RMR) techniques, at gate level and using fault-free decision gates, showing that the redundancy factor can be reduced by a factor of two to three using the proposed four-layer architecture, in replacement of RMR, thus enabling significant savings in the area, and power dissipation. The analysis of the reliability of averaging techniques together with the redundancy optimization has been performed for the first time in the context of a large-scale system, showing that a target reliability can be achieved with low redundancy factors (R < 8) for moderate defect densities (device failure rate up to 10 −5 ). The performed analysis of the optimal size of the reliable islands (clusters) supports the assumption that clustering needs to be applied at the lower levels of design abstraction hierarchy, especially for fabrication technologies with increased defect density.Index Terms-Fault-tolerant architecture, high defect density, redundancy, reliability of nanoelectronic systems.1536-125X/$25.00

An SET hardened dual-modular majority voter circuit for TMR system

“…As we know, TMR is widely used for SET mitigation [5]. The voter is an essential part in a TMR system.…”

“…Nowadays, reliability is emerging as an important parameter in deep submicron electronic technologies. As a consequence, different fault-tolerance techniques [9] also called hardening techniques used to guarantee correct operation even in the presence of faults have been studied over the past years [5]. In system level, we can utilize redundant unreliable components and majority voters [11] to construct a relatively reliable system.…”

Optimization of Nanoelectronic Systems Reliability Under Massive Defect Density Using Distributed R-fold Modular Redundancy (DRMR)

“…1) is a concept similar to RMR, where each output is connected to several voters/decision gates. The idea behind the concept is to increase the reliability of decision gates that are critical for fault-tolerance in RMR as demonstrated in [2], [6], [11]. N decision gates can operate in parallel, where N = 1, 2, ..., R. For N < R the efficiency of DRMR in terms of fault-tolerance is reduced (RMR is a special case of DRMR for N = 1).…”

“…The additional improvement of RMR and CRMR (cascaded RMR) techniques is possible by replacing the majority voter with an averaging and thresholding gate [10], [11]. A fault-tolerant technique named four-layer reliable architecture (4RLA) using R redundant units, averager and adaptable threshold shows notably better performance than RMR [10], [11].…”

“…A fault-tolerant technique named four-layer reliable architecture (4RLA) using R redundant units, averager and adaptable threshold shows notably better performance than RMR [10], [11]. Advanced fault-tolerant strategies must be developed in order to enable accommodating more than 10 12 molecular-sized devices on a 1 cm 2 chip [3].…”