An SET hardened dual-modular majority voter circuit for TMR system

Liu, Xiaopeng; Yan, Han; Zhang, Bin

doi:10.1587/elex.11.20131029

Cited by 5 publications

(3 citation statements)

References 14 publications

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“…2. Here, the TMR output is obtained as "AB+BC+CA" as a carry output of a full adder [8][9]. This subsystem can tolerate only one error.…”

Section: A the Existing 5-mr Configurationmentioning

confidence: 99%

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Fault Tolerant Design using 5-Modular Redundancy Configuration with Different Voter Circuits

Sasi¹

2019

CVRJST

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In the current situation, the reliability of a complex digital system is indigent owing to large amount of components, transistors, Integrated Circuits (ICs), etc. As a result the claim to design a good system with reliability is crucial. Such systems are frequently used in very critical applications such as bank transactions, defense communications, aerospace applications, etc. If these systems fail in the field, then the loss will be massive. The circuit designers carry on research to enhance the reliability of a system by adding redundancy like in hardware, software, information and time. The hardware redundancy is proposed to improve the reliability of the system. At present the Triple Modular Redundancy (TMR) is the most common technique used in the field of microelectronics to improve the reliability. This TMR system can tolerate one error for the correct output of the system. This paper primarily focuses on the 5MR scheme for the betterment of reliability which can tolerate two errors. The TMR in the 5MR system is implemented using FPGA Altera board with various voter circuits and ASIC implementation is carried out using ISCAS'85 and ISCAS'89 benchmark circuits. This paper analyze the 5MR system in detail using different majority computation circuits with TMR portion and convey the optimum circuit which will be suitable for low power, less area overhead and lesser delay.

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“…2. Here, the TMR output is obtained as "AB+BC+CA" as a carry output of a full adder [8][9]. This subsystem can tolerate only one error.…”

Section: A the Existing 5-mr Configurationmentioning

confidence: 99%

“…The majority function can also being implemented as {(A B)C}+ {AB} using the concept of CLA (Carry Lookahead Adder) circuit [8]. This circuit works as follows: i) If A = B = 1, then the majority output becomes 1.…”

Section: Dmodified Voter Using Carry Look-ahead Adder Principlementioning

confidence: 99%

Fault Tolerant Design using 5-Modular Redundancy Configuration with Different Voter Circuits

Sasi¹

2019

CVRJST

View full text Add to dashboard Cite

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“…The second approach is a fault-tolerant design in which the hardware redundancy is used to produce a fault-free response, and hence, the reliability is improved. The faults are expected to occur during the computation and are nullified due to redundancy (Kshirsagar and Patrikar, 2009;Smith, 2013;Liu et al, 2014). In TMR method, apart from the original module, two more similar modules are placed.…”

Section: Figure 1 Tmr System Configurationmentioning

confidence: 99%

Area, delay and power comparison of fault-tolerant systems with TMR using different voter circuits

Elamaran

Upadhyay

2017

IJSISE

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In a current very large-scale integration (VLSI) technology evolution, the reliability issues are the major concern for the improvement of the system. The most fundamental method used for the fault-tolerant system is triple modular redundancy (TMR) in which the majority voter circuit is used to obtain the fault-free response. In this study, the different voter circuits are implemented to analyse the least layout area and lower power dissipation with an applicationspecific integrated circuits (ASIC) approach using the Microwind layout editor tool. This work is carried out with the eight voting circuits including two proposed methods. The application examples such as a 32-bit adder, an unsigned 8x8 array multiplier, bitwise XOR operation and a 3 x 3 high-pass filter are demonstrated to compare the performance of different voters. The simulation results (power, area, delay) for all the four application examples are obtained and compared.

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Fault-tolerant medical imaging system with quintuple modular redundancy (QMR) configurations

Abdulhay

Elamaran

Arunkumar

et al. 2018

J Ambient Intell Human Comput

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An SET hardened dual-modular majority voter circuit for TMR system

Cited by 5 publications

References 14 publications

Fault Tolerant Design using 5-Modular Redundancy Configuration with Different Voter Circuits

Fault Tolerant Design using 5-Modular Redundancy Configuration with Different Voter Circuits

Area, delay and power comparison of fault-tolerant systems with TMR using different voter circuits

Fault-tolerant medical imaging system with quintuple modular redundancy (QMR) configurations

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