A modular VLIW Processor

Brost, Vincent; Yang, Fan; Paindavoine, Michel

doi:10.1109/iscas.2007.378669

Cited by 8 publications

(5 citation statements)

References 6 publications

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“…Later, similar projects were presented, e.g. a modular VLIW processor [19], the ρ-VEX, a reconfigurable and extensible soft-core VLIW processor based on the VEX ISA [20] or a native Java VLIW processor [21]. But these soft-core processors are focused on performance or the presences of a good software tool chain.…”

Section: Related Workmentioning

confidence: 99%

A Tiny Scale VLIW Processor for Real-Time Constrained Embedded Control Tasks

Stecklina

Methfessel

2014

2014 17th Euromicro Conference on Digital System Design

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In this paper we present the architectural design of the tiny scale very long instruction word (VLIW) soft-core processor TinyVLIW8. The processor is designed to achieve a minimal instruction execution time and design size. Although, the instruction repertoire is not large, it is adequate for control tasks, which require decision making that could not easily be implemented in an application specific integrated circuit (ASIC) and in which an extensive mathematical processing is not required. Especially in the area of embedded control tasks with real-time requirements an architecture using singlecycle instructions is key. We will illustrate an application of our TinyVLIW8 by presenting an design of a secure wake-up receiver for low power wireless sensor nodes. To the best of our knowledge, the presented soft-core processor is the smallest VLIW design with an average instruction execution time of one clock cycle only. The core consumes less than 6 % of the logic cells of the smallest Altera Cyclone IV FPGA and can be used in a system-on-chip design as well.

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Section: Related Workmentioning

confidence: 99%

A Tiny Scale VLIW Processor for Real-Time Constrained Embedded Control Tasks

Stecklina

Methfessel

2014

2014 17th Euromicro Conference on Digital System Design

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“…Due to the licensed Altera NIOS-II softcore, this VLIW design is not much flexible as well as not open source. Modular and configurable VLIW processor designs are presented in [10] [11] and [12]. The lack of a good software toolchain in each of these cases limited their use.…”

Section: Related Workmentioning

confidence: 99%

Dynamically reconfigurable register file for a softcore VLIW processor

Wong¹,

Anjam²,

Nadeem³

2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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This paper presents dynamic reconfiguration of a register file of a Very Long Instruction Word (VLIW) processor implemented on an FPGA. We developed an open-source reconfigurable and parameterizable VLIW processor core based on the VLIW Example (VEX) Instruction Set Architecture (ISA), capable of supporting reconfigurable operations as well. The VEX architecture supports up to 64 multiported shared registers in a register file for a single cluster VLIW processor. This register file accounts for a considerable amount of area in terms of slices when the VLIW processor is implemented on an FPGA. Our processor design supports dynamic partial reconfiguration allowing the creation of dedicated register file sizes for different applications. Therefore, valuable area can be freed and utilized for other implementations running on the same FPGA when not the full register file size is needed. Our design requires 924 slices on a Xilinx Virtex-II Pro device for dynamically placing a chunk of 8 registers, and places registers in multiples of 8 registers to simplify the design. Consequently, when 64 registers is not needed at all times, the area utilization can be reduced during run-time.

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“…Additionally, the design is not run-time reconfigurable. In [5], a modular design of a VLIW processor is reported. Certain parameters of the processor architecture could be altered in a modular fashion.…”

Section: Related Workmentioning

confidence: 99%

A VLIW softcore processor with dynamically adjustable issue-slots

Anjam

Nadeem

Wong

2010

2010 International Conference on Field-Programmable Technology

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Abstract-In this paper, we present a very long instruction word (VLIW) softcore processor implemented in an FPGA. The processor instruction set architecture (ISA) is based on the VEX ISA. The issue-width of the processor can be dynamically adjusted. The processor has two 2-issue cores, which can be run independently. If not in use, each core can be taken to a lower power mode by gating off the source clock. The two 2-issue cores can be combined at run-time to form one larger 4-issue core. Applications/kernels with larger instruction level parallelism (ILP), such as matrix multiplication, FFT, DFT, etc., can be run on the larger 4-issue core to exploit the available ILP. Applications with more data level parallelism (DLP), such as AES encryption/decryption, ADPCM encode/decode etc., can be run on the two 2-issue cores with the data divided among the two cores. We utilize the Xilinx partial reconfiguration flow to implement our design. The size of the partial bitstreams to combine the two 2-issue cores to one 4-issue core or split vice versa is 59 kbytes. The minimum time required to reconfigure the processor or adjust the issue-slots are 0.893 ms and 0.148 ms for the Xilinx Virtex-II Pro and Virtex-4 FPGAs, respectively.

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A modular VLIW Processor

Cited by 8 publications

References 6 publications

A Tiny Scale VLIW Processor for Real-Time Constrained Embedded Control Tasks

A Tiny Scale VLIW Processor for Real-Time Constrained Embedded Control Tasks

Dynamically reconfigurable register file for a softcore VLIW processor

A VLIW softcore processor with dynamically adjustable issue-slots

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