A monolithic CMOS 10 MHz DPLL for burst-mode data retiming

Sonntag, J.; Leonowich, R.H.

doi:10.1109/isscc.1990.110191

Cited by 29 publications

(10 citation statements)

References 2 publications

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“…Consequently, the maximum tolerable frequency error, referred to as frequency tolerance, directly depends on the maximum rate of phase change. It is easily calculated to be (1) where is the resolution of the phase interpolator, is the update period of the state machine, DF is the decimation factor used to reduce the dithering jitter to one phase step, and is the transition density defined with respect to a period of . Substituting typical parameters of , , , and , where is equal to the incoming bit period, results in a maximum frequency tolerance of about 490 parts per million (ppm).…”

Section: A Dual-loop Cdrmentioning

confidence: 99%

“…As indicated by (1) and (2), both the frequency tolerance and the tracking bandwidth can be improved by increasing the step size of the interpolator. 1 This requirement contradicts the need for a smaller phase step to minimize dithering jitter. In addition to the conflicting requirements on the interpolator step size, the dual-loop CDR also requires additional hardware to generate multiple equally spaced clock phases.…”

Section: A Dual-loop Cdrmentioning

confidence: 99%

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A Wide-Tracking Range Clock and Data Recovery Circuit

Hanumolu

Wei

Moon

2008

IEEE J. Solid-State Circuits

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Abstract-A hybrid analog-digital quarter-rate clock and data recovery circuit (CDR) that achieves a wide-tracking range and excellent frequency and phase tracking resolution is presented in this paper. A split-tuned analog phase-locked loop (PLL) provides eight equally spaced phases needed for quarter-rate data recovery and the digital CDR loop adjusts the phase of the PLL output clocks in a precise manner to facilitate plesiochronous clocking. The CDR employs a second-order digital loop filter and combines delta-sigma modulation with the analog PLL to achieve sub-picosecond phase resolution and better than 2 ppm frequency resolution. A test chip fabricated in a 0.18 m CMOS process achieves BER 10 and consumes 14 mW power while operating at 2 Gb/s. The tracking range is greater than 5000 ppm and 2500 ppm at 10 kHz and 20 kHz modulation frequencies, respectively, making this CDR suitable for systems employing spread-spectrum clocking.Index Terms-Clock and data recovery, phase-locked loop (PLL), spread-spectrum clocking, digital phase interpolation, delta-sigma.

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Section: A Dual-loop Cdrmentioning

confidence: 99%

Section: A Dual-loop Cdrmentioning

confidence: 99%

A Wide-Tracking Range Clock and Data Recovery Circuit

Hanumolu

Wei

Moon

2008

IEEE J. Solid-State Circuits

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“…Throughout the paper, we will be using the CDR circuit [1,2] shown in Figure 1 to illustrate the stochastic model and the performance evaluation techniques. The framework we present here is by no means restricted to this particular circuit, and the general model we describe can be used for other discrete-time mixed-signal processing circuits.…”

Section: Modeling and Performance Evaluationmentioning

confidence: 99%

Stochastic modeling and performance evaluation for digital clock and data recovery circuits

Demіr¹,

Feldmann²

2000

Proceedings of the Conference on Design, Automation and Test in Europe

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Clock and data recovery circuits are essential components in communication systems. They directly influence the bit-error-rate performance of communication links. It is desirable to predict the rate of occasional detection errors and the loss of synchronization due to the non-ideal operation of such circuits. In high-speed data networks, the bit-error-rate specification on the system can be very stringent, i.e., 10¢ 14 . It is not feasible to predict such error rates with straightforward, simulation based, approaches. This work introduces a stochastic model and an efficient, analysis-based, nonMonte-Carlo method for performance evaluation of digital data and clock recovery circuits. The analyzed circuit is modeled as finite state machines with inputs described as functions on a Markov chain state-space. System performance measures, such as probability of bit errors and rate of synchronization loss, can be evaluated through the analysis of a larger resulting Markov system. A dedicated multi-grid method is used to solve the very large associated linear systems. The method is illustrated on a real industrial clock-recovery circuit design.

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“…In other CDR architectures, the oversampling algorithm was applied. These usually adopt 1:N demultiplexing architectures for relaxing the processing speed after very high oversampling the input [5][6][7][8].…”

Section: Ntroductionmentioning

confidence: 99%

A Clock Recovery Circuit using Half-rate 4X-Oversampling PD

Jang

Lee

Kang

2005 IEEE International Symposium on Circuits and Systems

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In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4x oversampling phase detector (PD) structure is described. The PD is designed by 4X oversampling method. The PD finds the data_ lead and data _lag by the logical computation to the input data and controls amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. Proposed circuit is designed using the TSMC 0.25um CMOS technology and operating voltage is 2.5V. The circuit is operating between 480Mb/s -1.5Gb/s.

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A monolithic CMOS 10 MHz DPLL for burst-mode data retiming

Cited by 29 publications

References 2 publications

A Wide-Tracking Range Clock and Data Recovery Circuit

A Wide-Tracking Range Clock and Data Recovery Circuit

Stochastic modeling and performance evaluation for digital clock and data recovery circuits

A Clock Recovery Circuit using Half-rate 4X-Oversampling PD

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