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A 125Mbaud quad transceiver for lO/lOO fast ethernet has been designed in a 5V 0.35pm digital CMOS process. Power consumption for the device is 3W. Detailed testing show excellent receiver results with error free performance up to 160m under worst-case baseline wander and crosstalk conditions. The analog receiver uses digital adaptation circuitry to optimize an automatic gain control circuit with baseline wander correction, an equalizer and a DC offset correction circuit.

This paper describes behavioral models for mixed-mode and multi-level simulation of phase-locked loops(PLLs). PLLs are a difficult class of systems to evaluate using conventional circuit simulators because of the mixed analog digital signals involved, and extensively long runtimes required to capture the performance. Behavioral modeling techniques and a mixed-signal simulator, the AT&T Bell Laboratories ADAMS simulator, are used to overcome these limitations.An all analog PLL is simulated at the behavioral level to measure the lock-in characteristics as well as the tracking range. A high-speed digital PLL is simulated at the behavioral level, as well as at a multi-level using device-level models for the phase detector, to measure the lock-in time and detect false locking.

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