Behavioral Modeling Phase-locked Loops for Mixed-Mode Simulation

Antao, Brian A.; El-Turky, F.; Leonowich, R.H.

doi:10.1007/978-1-4613-1405-9_4

Cited by 5 publications

(10 citation statements)

References 16 publications

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“…In traditional approaches, the behavioral model only describes the transfer function of the loop filter or keeps the transistor-level descriptions [12]. As mentioned in [13], using transfer function only is not enough for accurate behavioral simulation. However, directly using the values of the RC components appearing in the specification may not be so accurate because the equivalent RC values often have variance after layout due to parasitic effects.…”

Section: B Charge Pump and Loop Filtermentioning

confidence: 99%

Systematic HDL Design of a S-? Fractional-N Phase-Locked Loop for Wireless Applications

Oualkadi

Flandre

2008

2008 IEEE Computer Society Annual Symposium on VLSI

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This paper presents a systematic HDL design of a ∑-∆ fractional-N Phase-Locked Loop based on behavioral modeling. The proposed design consists in describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the PLL system performances. The obtained results are compared with transistor-level simulations to validate the effectiveness of the proposed models.

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Section: B Charge Pump and Loop Filtermentioning

confidence: 99%

Systematic HDL Design of a S-? Fractional-N Phase-Locked Loop for Wireless Applications

Oualkadi

Flandre

2008

2008 IEEE Computer Society Annual Symposium on VLSI

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“…The combination of analog and digital elements in the architecture of CP-PLL arises complexity in the analysis of the whole loop [7], [8], [15]. The phase and frequency detector (PFD) and divider units belongs to digital part.…”

Section: Introductionmentioning

confidence: 99%

“…The charge-pump phase locked loop (CP-PLL) is an integrated subsystem used in various applications from radio frequency (RF) communication like FM modulation and demodulation, frequency synthesis and multiplication frequency discrimination, tone decoding, data synchronization and conditioning, voltage-to-frequency conversion and clock and data recovery, Doppler shift frequency [1], [4], [15]- [18]. The combination of analog and digital elements in the architecture of CP-PLL arises complexity in the analysis of the whole loop [7], [8], [15].…”

Section: Introductionmentioning

confidence: 99%

Simulations of 3<sup>rd</sup> order voltage switched CP-PLL using a fast event switching macromodeling

Ali

Rahajandraibe

Haddad

et al. 2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

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Abstact-The charge-pump phase-locked loop (CP-PLL) has gained an essential place in the wide area of the radio frequency (RF) communication and industrial electronics. Since it is a combination of analog and digital elements, it enhances the complexity to study the transient behavior of an arbitrary ordered CP-PLL using any general feedback system concept. Concerning the PLL circuit, particularity that operating with voltage switched charge pump (VSCP) supplements the peculiarity arising in the form of non-constant pump current. Whereas its characterization in transient time off-locking and on-locking region remains critical due to its unbalanced pumping characteristics. The linear models are valid for small phase errors in the locked state. However, transistor level models are very near to the real design but are constrained with timeinefficiency and computer resource consumption. In this paper, the transient behavior of the 3 rd order VSCP-PLL is investigated using an ultra-fast and resource efficient event-driven (ED) macro-modeling technique. Due to its inherent competency, the off-locking behavior of the system can easily be characterized. Related to the VSCP-PLL architecture, the ED model is simulated and some features are highlighted using piece-wise linear and non-linear VCO. Moreover, the work is extended to compare its performance with an equivalent PLL operating with a current switched charge-pump (CSCP) for a constant and ramp function of the reference frequency.Index Terms-CP-PLL, Event Driven Technique, voltage operated charge-pump, mixed-signal PLL system.

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“…Starting from the specifications of the system on top level, behavioral model simulation and optimization can be used to evaluate different architectures, which allows an earlier detection of design faults and provides a means by which the PLL system can be tested for its overall loop performance characteristics at a higher level prior to generating circuit-level realizations for the individual subsystem [4]. Once the architecture is selected, the following process is circuit sizing and final layout.…”

Section: Analog Hierarchical Designmentioning

confidence: 99%

“…Different behavioral models for PLL systems are presented for purely PLL simulation and verification [4][5][6][7]22]. A recent approach for hierarchical PLL design [17] focuses mainly on the jitter-power trade-off in the VCO design.…”

Section: Circuit Sizingmentioning

confidence: 99%

Fast automatic sizing of a charge pump phase-locked loop based on behavioral models

Zou¹,

Mueller²,

Graeb³

et al.

BMAS 2005. Proceedings of the 2005 IEEE International Behavioral Modeling and Simulation Workshop, 2005.

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In this paper, we present an analog hierarchical sizing methodology applied to a third-order charge pump phase-locked loop (CPPLL). The key idea is to propagate the specifications from the requirements of the behavioral level to the circuit level. At the behavioral level, the performance is optimized while considering the potential capacity of the underlying circuits. Critical advantage of the illustrated methodology is a shortened PLL sizing process due to the use of fast-simulating models at behavioral level. The simulation results show the availability of this method on the CPPLL which makes an automatic sizing process actually feasible in terms of computation time.

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Behavioral Modeling Phase-locked Loops for Mixed-Mode Simulation

Cited by 5 publications

References 16 publications

Systematic HDL Design of a S-? Fractional-N Phase-Locked Loop for Wireless Applications

Systematic HDL Design of a S-? Fractional-N Phase-Locked Loop for Wireless Applications

Simulations of 3<sup>rd</sup> order voltage switched CP-PLL using a fast event switching macromodeling

Fast automatic sizing of a charge pump phase-locked loop based on behavioral models

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