Systematic HDL Design of a S-? Fractional-N Phase-Locked Loop for Wireless Applications

Abstract

This paper presents a systematic HDL design of a ∑-∆ fractional-N Phase-Locked Loop based on behavioral modeling. The proposed design consists in describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the PLL system performances. The obtained results are compared with transistor-level simulations to validate the effectiveness of the proposed models.