Behavioral modeling phase-locked loops for mixed-mode simulation

SUMMARYWe present a low-supply voltage (2 V) low-power consumption (500 W) analogue phase-locked loop (PLL), working at two low frequencies (1 and 10 kHz), to be used in an integrated lock-in ampliÿer. An externally settable control bit allows the switching operation between the two di erent frequencies. The circuit has been designed in a standard 0.6 -m CMOS technology and di ers from the standard analogue PLL architectures for the current mode implementation of both the loop ÿlter and of the oscillator. Three di erent locked waveforms (sinusoidal, triangular, squared) can be obtained at the PLL output. Simulation results, obtained through the use of PSPICE and using accurate transistor models, will be proposed. The pull-in ranges are about ±250 Hz around 1 and ±1:3 kHz around 10 kHz, with pull-in times of about 10 and 4 ms, respectively.

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A current‐mode 1kHz/10kHz low‐voltage integrated analogue PLL for lock‐in portable applications

Ferri

Massa

2003

Circuit Theory & Apps

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A formulation for analog behavioral-level sensitivity and steady-state analysis

Antao

Brodersen

1996

Analog Integr Circ Sig Process

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PLL low pass filter design considering unified specification constraints

Jiang

Xia

Wang

2014

Analog Integr Circ Sig Process

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Behavioral modeling phase-locked loops for mixed-mode simulation

Cited by 20 publications

References 20 publications

A current‐mode 1kHz/10kHz low‐voltage integrated analogue PLL for lock‐in portable applications

A current‐mode 1kHz/10kHz low‐voltage integrated analogue PLL for lock‐in portable applications

A formulation for analog behavioral-level sensitivity and steady-state analysis

PLL low pass filter design considering unified specification constraints

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