A monolithic CMOS maximum-likelihood convolutional decoder for digital communication systems

Hoppes, P.; Mccallister, R. D.

doi:10.1109/isscc.1982.1156363

Cited by 4 publications

(2 citation statements)

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“…The first uses a node parallel approach with individual ACS processing units dedicated to each node [4,5,6,7]. Each processing unit performs bit parallel operations with 6 to 8 bits.…”

Section: A Bit-serial Architecturementioning

confidence: 99%

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A modular bit-serial architecture for large constraint length Viterbi decoding

Bree

Dodds

Bolton

et al. 1990

IEEE International Conference on Communications, Including Supercomm Technical Sessions

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This paper presents a node-parallel Viterbi decoding architecture with bit-serial processing and communication. This structure allows short constraint length decoders to be expanded, without loss of throughput, to implement a Viterbi decoder of larger constraint length. Wiring of the decoder models the encoder trellis and a variety of generating codes can be accommodated by appropriate wiring of the decoder. Bit-serial communication between processing nodes requires only a single wire and thus on chip and off chip wiring requirements are quite small. A constraint length K=4 "proof of concept" chip was developed using 9860 transistors in 3 pm CMOS. The circuit supports any rate 1/2 or 1/3 code with 8 level soft decision. Performance measurements on two rate 1/2 interconnected chips confirm the expected 3.8 dB coding gain at 10-4 error rate.

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“…The first uses a node parallel approach with individual ACS processing units dedicated to each node [4,5,6,7]. Each processing unit performs bit parallel operations with 6 to 8 bits.…”

Section: A Bit-serial Architecturementioning

confidence: 99%

“…3(a). In conventional implementations [4,5,6,7], a node processor is associated with each "next" node in the trellis as shown in Fig. 3(b).…”

Section: Pairing Of Node Processorsmentioning

confidence: 99%