A Monolithic Three-Axis Accelerometer with Wafer-Level Package by CMOS MEMS Process

Abstract

This paper presents a monolithic three-axis accelerometer with wafer-level package by CMOS MEMS process. The compositions of the microstructure are selected from CMOS layers in order to suppress the in-plane and out-of-plane bending deflection caused by the residual stresses in multiple layers. A switched-capacitor sensing circuit with a trimming mechanism is used to amplify the capacitive signal, and decrease the output dc offset voltage to ensure the desired output voltage swing. The CMOS MEMS wafer is capped with a silicon wafer using a polymer-based material. The measured sensitivities with and without a wafer-level package range from 113 mV/G to 124 mV/G for the in-plane (x-axis, y-axis) accelerometer, and from 50 mV/G to 53 mV/G for the z-axis accelerometer, respectively.

Implementation of a CMOS/MEMS Accelerometer with ASIC Processes

“…For 3-axis integrated accelerometer design, the z -axis sensing element consists of an imbalanced proof mass, a torsional spring beam and comb fingers on both ends of the proof mass [13]. Using three individual sensing units to detect the tri-axis acceleration can reduce structural curling [14]. A single proof-mass tri-axis accelerometer can significantly reduce the chip size and improve the accelerometer sensitivity [15,16].…”

A Bond-Wire Drift Offset Minimized Capacitance-to-Digital Interface for MEMS Accelerometer with Gain-Enhanced VCO-Based Quantization and Nested Digital Chopping Feedback Loops

“…In addition, an output offset caused by nonideal factors [ 16 , 18 ] (e.g., the bond-wire capacitance drift) is considerable. To address the issue, an offset minimization loop with electrostatic spring constant modulation was proposed in [ 14 ].…”