A multi-cycle fixed point square root module for FPGAs

Campo, Fernando Martin del; Morales-Reyes, Alicia; Perez-Andrade, Roberto; Cumplido, René; Orozco-Lugo, A.G.; Feregrino, Claudia

doi:10.1587/elex.9.971

Cited by 10 publications

(5 citation statements)

References 6 publications

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“…An algorithm in ref. [10] uses a distributed memory in which precalculated values of the square root are stored. As the memory size decreases, the number of calculation iterations increases.…”

Section: Initial Parameters For the Set Of Considered Options Amentioning

confidence: 99%

A Configurable IP Core for Calculating the Integer Square Root for Serial and Parallel Implementations in FPGA

Matyukha¹,

Voloshchuk²,

Mosin

2022

Electronics

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The development of digital technologies is in many ways associated with an improvement of integrated technologies, microelectronic components, and the capabilities of hardware acceleration of the most computationally complex operations. Field-programmable gate arrays (FPGAs) are actively used for prototyping or the small-scale production of special purpose digital signal processing (DSP) devices. The implementation of DSP algorithms is variative in nature and affects important indicators of a produced device, such as the accuracy of the numerical solution, performance, structural/functional complexity, etc. The architectural features of the FPGA can be used for choosing an effective DSP algorithm in the form of solving the multicriteria discrete optimization problem. This paper analyzes and selects an effective algorithm for calculating the integer square root, which is one of the most frequently used digital signal processing operations. A behavioral model based on a non-restoring algorithm is presented. The SystemVerilog description of the module for calculating the square root, presented in the form of a universal configurable IP core, has been developed and synthesized. The configuration allows one to change the width of the input data bus and select the serial or parallel processing mode for scalar or vector data. The results of testing and comparison of the obtained characteristics with the corresponding Xilinx Cordic IP core are presented. The field test of the proposed IP core implemented in the Xilinx FPGA SOC xc7z045ffg900-2 has demonstrated the gain in the maximum system frequency at 174 MHz in the sequential mode with a 48-bit input bus and 169 MHz in the pipelined mode at a reduction of both the structural complexity and the number of used FPGA internal resources in comparison with the Xilinx Cordic IP core.

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Section: Initial Parameters For the Set Of Considered Options Amentioning

confidence: 99%

A Configurable IP Core for Calculating the Integer Square Root for Serial and Parallel Implementations in FPGA

Matyukha¹,

Voloshchuk²,

Mosin

2022

Electronics

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“…Approximate computing is considered as a promising approach to design of area-, performance-or power-efficient circuits for applications which are resistant to a certain amount of computational inaccuracy. Approximate calculation circuits have been actively surveyed [2][3][4][5]. According to the work in [6] and [7], which investigated the recent studies in the area of approximate computing, the design of approximate multipliers has extensively been studied.…”

Section: Introductionmentioning

confidence: 99%

A design methodology for approximate multipliers in convolutional neural networks: A case of MNIST

Shirane

Yamamoto

Tomiyama

2021

IJRES

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In this paper, we present a case study on approximate multipliers for MNIST Convolutional Neural Network (CNN). We apply approximate multipliers with different bit-width to the convolution layer in MNIST CNN, evaluate the accuracy of MNIST classification, and analyze the trade-off between approximate multiplier’s area, critical path delay and the accuracy. Based on the results of the evaluation and analysis, we propose a design methodology for approximate multipliers. The approximate multipliers consist of some partial products, which are carefully selected according to the CNN input. With this methodology, we further reduce the area and the delay of the multipliers with keeping high accuracy of the MNIST classification.

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“…Arithmetic element functions (reciprocal, square root and inverse square root) are playing very important roles in digital signal processing, multimedia and scientific computing. So far, most of the researches are focused on reciprocal [1] and square root [2]- [4]. Other reports are concentrated on inverse square root [5]- [9], which plays a significant role not only in vector normalization, least squares lattice filters, Cholesky decomposition and Givens rotation, but also in 3D graphics application and compressed imaging [10].…”

Section: Introductionmentioning

confidence: 99%

Hardware Implementation of Single Iterated Multiplicative Inverse Square Root

Luo¹,

Huang²,

Luo³

et al. 2017

ElAEE

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Inverse square root has played an important role in Cholesky decomposition, which devoted to hardware efficient compressed sensing. However, the performance is usually limited by the trade-off between throughput and precision. This paper presents hardware implementation of fixed-point single iterated multiplicative inverse square root. Multiple piecewise linear approximation in softly nonlinear range is used to compute the initial value. Single iterated Newton-Raphson method is employed to obtain high precision. Multiple constants multiplication technique is proposed to achieve high throughput. The combination of these techniques yields high performance in terms of throughput and precision. It obtains more than 70 % of throughput improvement and almost 100 × higher precision over the inverse square root Intellectual Property (IP) from Altera. In addition, Cholesky decomposition has been presented to validate the proposed architecture, which shows that 42 % of throughput improvement is achieved compared with the IP.

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A multi-cycle fixed point square root module for FPGAs

Cited by 10 publications

References 6 publications

A Configurable IP Core for Calculating the Integer Square Root for Serial and Parallel Implementations in FPGA

A Configurable IP Core for Calculating the Integer Square Root for Serial and Parallel Implementations in FPGA

A design methodology for approximate multipliers in convolutional neural networks: A case of MNIST

Hardware Implementation of Single Iterated Multiplicative Inverse Square Root

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