A multi-level design methodology of multistage interconnection network for MPSOCs

Aydi, Yassine; Baklouti, Mouna; Abid, Mohamed; Dekeyser, Jean-Luc

doi:10.1504/ijcat.2011.045406

Cited by 8 publications

(2 citation statements)

References 31 publications

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“…Additionally, the temporary registers implanted in shared buses usually consume a greater area and higher energy levels, resulting in poor scalability. This is likely to stand as a major hindrance to the maintenance of effective communication via future Multi-Processor Systems on Chip (MPSoC) designs [24][25][26][27][28]. To cater to these needs, Multistage Interconnection Networks (MINs) have emerged as a potential solution for the increasing demand for scalability and reliability in static Network-on-chip (NoC) architectures, to meet the exponential growth in massive parallel computing.…”

Section: Related Workmentioning

confidence: 99%

Mapping of Deep Neural Network Accelerators on Wireless Multistage Interconnection NoCs

Aydi,

Mnejja,

Mohammed

et al. 2023

Applied Sciences

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In the last few decades, the concept of Wireless Network-on-chip (WiNoC) has emerged as a promising alternative for Multiprocessor Systems on Chip (MPSOC) to achieve reliable and scalable communication. Worth recalling in this regard is that our research team has already designed, verified and evaluated Multistage Interconnection Networks (MIN) in this field. With respect to the present work, we consider proceeding with further exploring our thoughts on this research area. Firstly, we propose the design and performance evaluation of a hybrid (wireless/wired) MIN, analysing how this augmented network can potentially improve not only the average delay, but also energy consumption. Secondly, we continue with examining the implementation of our advanced DELTA-based MIN architecture on Deep Neural Network (DNN) accelerators, while accounting for its potential regularity and scalability in simultaneously maintaining an effective power efficiency and lower latency throughout the DNN operating process. In this context, several metrics have been evaluated in regard to three DNN application cases through implementation of their main respective modules.

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Section: Related Workmentioning

confidence: 99%

Mapping of Deep Neural Network Accelerators on Wireless Multistage Interconnection NoCs

Aydi,

Mnejja,

Mohammed

et al. 2023

Applied Sciences

Self Cite

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“…However, accesses from different sources to different targets never introduce contentions. Interconnect types allowing this are the full crossbars and the multi-stage interconnection network [31] such as the omega networks, the delta networks, or the related logarithmic interconnect [32]. The experiments of this paper use a full crossbar interconnect.…”

Section: B Modifications Of the Tile Structurementioning

confidence: 99%

Reconciling performance and predictability on a many-core through off-line mapping

Carle

Djemal

Genius

et al. 2014

2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

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Abstract-We start from a general-purpose many-core architecture designed for average-case performance and ease of use. In particular, its distributed shared memory programming model allows the use of a code generation flow based on the (unmodified) gcc compiler chain. We modify this architecture and extend the code generation flow to allow the construction of efficient hard real-time systems starting from dependent task specifications. We rely on a static (off-line) real-time scheduling paradigm welladapted to embedded control and signal processing applications with regular control structure.We modify the architecture (and in particular the on-chip network) to allow the implementation of static schedules with very high (clock cycle) temporal precision. On the software side, we define application mapping rules ensuring that the timing precision provided by the hardware is not lost. These mapping rules include requirements on the allocation of data variables to specific RAM banks and on the use of locks to ensure the absence of contentions during access to shared resources. Applications complying with these rules can be written manually or automatically obtained using a new mapping tool that takes all the allocation and scheduling decisions. Compilation of the resulting C code is still done using the (unmodified) gcc compiler chain. The resulting platform provides good performance, and at the same provides very high timing precision, as shown by two case studies (an embedded controller and an implementation of the FFT).We conclude our paper with a presentation of some ongoing work on the subject: A case study (an implementation of the H.264 decoder) meant to test the limitations of our method.

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Exploring Hybrid NoC Architecture for Chip Multiprocessor

Mnejja¹,

Aydi²,

Abid³

2018

2018 30th International Conference on Microelectronics (ICM)

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A multi-level design methodology of multistage interconnection network for MPSOCs

Cited by 8 publications

References 31 publications

Mapping of Deep Neural Network Accelerators on Wireless Multistage Interconnection NoCs

Mapping of Deep Neural Network Accelerators on Wireless Multistage Interconnection NoCs

Reconciling performance and predictability on a many-core through off-line mapping

Exploring Hybrid NoC Architecture for Chip Multiprocessor

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