A multi-level parallel simulation approach to electron transport in nano-scale transistors

Abstract

Physics-based simulation of electron transport in nanoelectronic devices requires the solution of thousands of highly complex equations to obtain the output characteristics of one single input voltage. The only way to obtain a complete set of bias points within a reasonable amount of time is the recourse to supercomputers offering several hundreds to thousands of cores. To profit from the rapidly increasing availability of such machines we have developed a state-of-the-art quantum mechanical transport simulator dedicated to nanodevices and working with four levels of parallelism. Using these four levels we demonstrate that an almost ideal scaling of the walltime up to 32768 processors with a parallel efficiency of 86% is reached in the simulation of realistically extended and gated field-effect transistors.Obtaining the current characteristics of these devices is reduced to some hundreds of seconds instead of days on a small cluster or months on a single CPU.

Atomistic Full-Band Design Study of InAs Band-to-Band Tunneling Field-Effect Transistors

“…The calculation of electrostatic potential and of electron and hole populations are self-consistently coupled and parallelized to reduce the simulation time [16]. The transport direction x is aligned with the 100 crystal axis where the highest BTBT probability is expected.…”

On the Validity of the Top of the Barrier Quantum Transport Model for Ballistic Nanowire MOSFETs

“…A critical element in the model is the representation of the device in an atomistic TightBinding (TB) model [6], which understands the finite number of atoms in the structure, their local arrangement with details such as strain distribution and disorder [7,8]. A full 3D atomistic quantum transport model [9,10,11] can provide the device characteristics, however, this model is computationally time consuming [12]. Recently, a 2D top of the barrier (ToB) atomistic quantum transport model [13,14,15] has been used for speedy simulation and analysis of SiNW FET device characteristics, which provides significant insight.…”

Advancing nanoelectronic device modeling through peta-scale computing and deployment on nanoHUB

“…Additionally, NEMO 3-D is prepared with programmable multiple-level parallelization (Figure 3) which is similar to the tri-level parallelism in NEMO 1-D (bias-energy-momentum) [22] and fourlevel parallelism in OMEN (bias-energy-momentum-1D spatial decomposition) [23][24]. However the parallelization scheme is different in a sense that the variables involved in each level can determined depending on the application.…”