A multi-objective genetic algorithm for on-chip real-time optimisation of word length and power consumption in a pipelined FFT processor targeting a MC-CDMA receiver

Sulaiman, Nasir; Arslan, Tughrul

doi:10.1109/eh.2005.4

Cited by 8 publications

(4 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Sulaimal et al [24] presented a multi‐objective genetic algorithm (GA) for real‐time optimisation of word‐length in a fast Fourier transform (FFT) processor. This is one of the rare works that consider the word length issue in processor architecture.…”

Section: Related Workmentioning

confidence: 99%

Accuracy‐aware processor customisation for fixed‐point arithmetic

Vakili¹,

Langlois²,

Bois³

2016

IET Computers & Digital Techniques

View full text Add to dashboard Cite

Section: Related Workmentioning

confidence: 99%

Accuracy‐aware processor customisation for fixed‐point arithmetic

Vakili¹,

Langlois²,

Bois³

2016

IET Computers & Digital Techniques

View full text Add to dashboard Cite

“…Leban and Tasic [24] used mean square error, delay, and area as objectives. Signal-to-noise ratio and power are used as objectives by Sulaiman and Arslan [25]. These approaches employed a weighted sum as a fitness function.…”

Section: E Wordlength Optimization With Multi-objective Evolutionarymentioning

confidence: 99%

Automatic Floating-Point to Fixed-Point Transformations

Han

Olson

Evans

2006

2006 Fortieth Asilomar Conference on Signals, Systems and Computers

View full text Add to dashboard Cite

Abstract-Many digital signal processing and communication algorithms are first simulated using floating-point arithmetic and later transformed into fixed-point arithmetic to reduce implementation complexity. For the floating-point to fixed-point transformation, this paper describes two methods within an automated transformation environment. The first method, a gradientbased search for single-objective optimization with sensitivity information, provides a single solution, and can become trapped in local optima. The second method, a genetic algorithm for multiobjective optimization, provides a family of solutions that form a tradeoff curve for signal quality vs. implementation complexity. We provide case studies for an infinite impulse response filter. In the case study, implementation complexity is lookup table area for a field programmable gate array (FPGA) realization. We have made the transformation methods available in a software release on the Web.

show abstract

“…Sulaiman and Arslan [14] presented a Multi Objective Genetic Algorithm (MOGA) for WL and power consumption in a Fast Fourier Transform (FFT) processor. The GA was used to find FFT coefficients which have optimum performance in terms of Signal to Noise Ratio (SNR) and power consumption.…”

Section: Introductionmentioning

confidence: 99%

Multiple-Width Bus Partitioning Approach to Datapath Synthesis

Ahmadi

Zwoliński

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

Abstract-A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of Functional Units has a great impact on design costs. A combination of both methods is used in this paper in the form of a partitioned shared bus structure, in which every partition has a different width and all the functional units connected to a bus partition have the same input/output word-lengths. Having controlled the group binding and word-length of the FUs as well as the other synthesis parameters, a high-level synthesis tool is introduced to implement DSP algorithms in digital hardware. The tool uses a MultiObjective Optimization Genetic Algorithm to minimize the circuit area, delay, power consumption and digital noise by selecting an optimal grouping and word-length for each FU in a shared bus system. Results demonstrate that savings can be made in the overall system costs by applying this method.

show abstract

A multi-objective genetic algorithm for on-chip real-time optimisation of word length and power consumption in a pipelined FFT processor targeting a MC-CDMA receiver

Cited by 8 publications

References 17 publications

Accuracy‐aware processor customisation for fixed‐point arithmetic

Accuracy‐aware processor customisation for fixed‐point arithmetic

Automatic Floating-Point to Fixed-Point Transformations

Multiple-Width Bus Partitioning Approach to Datapath Synthesis

Contact Info

Product

Resources

About