A multigigabit backplane transceiver core in 0.13-/spl mu/m CMOS with a power-efficient equalization architecture

Design Techniques for High-Speed I/Os: Challenges and Opportunities

“…All need to be completed within one UI for tap-1. Loop-unrolling has been proven to be an effective technique in meeting the timing constraint of the tap-1 of DFE [19,[58][59][60]. High-order loop-unrolling also emerged when data rate exceeds 10 Gb/s, however, at the cost of high silicon consumption [10,11,61].…”

A 6-Gb/s Differential Voltage Mode Driver with Independent Control of Output Impedance and Pre-Emphasis Level

“…For output impedance control, a voltage mode driver is usually implemented with multiple slices which are enabled selectively to get the desired output impedance [5,6]. As the data rate increases, the inter-symbol interference (ISI) becomes much more sever and the signal equalization of a receiver may not be sufficient to get enough eye opening and the pre-emphasis of transmitted signal level is often required.…”

On-chip data communication : analysis, optimization and circuit design

“…In such pre-emphasis schemes, delayed copies of the symbols are weighted and summed to create equalizing finite impulse response (FIR) filters [97,98,[111][112][113][114][115][116][117].…”

“…A motivation to use DFE instead of linear equalization is that DFE does not amplify crosstalk [112]. But DFE with more than a few taps tends to become complex and power hungry, so it is sometimes combined with a linear equalizer [111,112,116,137,138].…”

“…But DFE with more than a few taps tends to become complex and power hungry, so it is sometimes combined with a linear equalizer [111,112,116,137,138]. An often stated motivation is that linear equalizers can cancel long tails in the symbol response with lower complexity.…”