A multimedia 32 b RISC microprocessor with 16 Mb DRAM

Shimizu, Toshihisa; Korematu, J.; Satou, M.; Kondo, Hiroyuki; Iwata, S.; Sawai, Katsunori; Okumura, N.; Ishimi, K.; Nakamoto, Y.; Kumanoya, M.; Dosaka, K.; Yamazaki, Akira; Ajioka, Y.; Tsubota, Hiroyuki; Nunomura, Yasuhiro; Urabe, T.; Hinata, J.; Saitoh, Kazunori

doi:10.1109/isscc.1996.488577

Cited by 44 publications

(7 citation statements)

References 1 publication

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“…From the Equation (1), when V dd approaches the threshold voltage, V t , the delay increases drastically [4], as shown in Figure 2. Obviously, using this method causes the performance loss on the speed.…”

Section: A) Supply Voltage Scalingmentioning

confidence: 96%

“…Reducing the supply voltage can significantly reduce the power dissipation that is a quadratic function of the operating voltage. This is illustrated in Figure 1, it represents the power consumption as a function of V dd for a 4-bit carry look-ahead adder in 0.18 μm process technology [3] [4]. The supply voltage for various logic functions and logic styles are dependence on the power consumption.…”

Section: A) Supply Voltage Scalingmentioning

confidence: 99%

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Ultra-Low Power Designing for CMOS Sequential Circuits

Sreenivasulu¹,

Rao²,

Babu³

2015

IJCNS

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Power consumption is the bottleneck of system performance. Power reduction has become an important issue in digital circuit design, especially for high performance portable devices (such as cell phones, PDAs, etc.). Many power reduction techniques have also been proposed from the system level down to the circuit level. High-speed computation has thus become the expected norm from the average user, instead of being the province of the few with access to a powerful mainframe. Power must be added to the portable unit, even when power is available in non-portable applications, the issue of low-power design is becoming critical. Thus, it is evident that methodologies for the design of high-throughput, low-power digital systems are needed. Techniques for low-power operation are shown in this paper, which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. The threshold voltages of the MTCMOS devices for both low and high Vth are constructed as the low threshold Vth is approximately 150 -200 mv whereas the high threshold Vth is managed by varying the thickness of the oxide Tox. Hence we are using different threshold voltages with minimum voltages and hence considered this project as ultra-low power designing.

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Section: A) Supply Voltage Scalingmentioning

confidence: 96%

Section: A) Supply Voltage Scalingmentioning

confidence: 99%

Ultra-Low Power Designing for CMOS Sequential Circuits

Sreenivasulu¹,

Rao²,

Babu³

2015

IJCNS

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“…Merging a processor and memory on the same die [12] is the first step in using this internal memory bandwidth. To fully utilize this bandwidth, however, the application-accessible width of the datapath should be close to the number of memory columns.…”

Section: A Architecturementioning

confidence: 99%

Design of a 3-D fully depleted SOI computational RAM

Koob

Leder²,

Sung

et al. 2005

IEEE Trans. VLSI Syst.

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We introduce a three-dimensional (3-D) processorin-memory integrated circuit design that provides progressively increasing processing power as the number of stacked dies increases, while incurring no extra design effort or mask sets. Innovative techniques for processor/memory redundancy and fast global bus evaluation are described. The architecture can be augmented with a nearest-neighbor physical 3-D communications network that can substantially reduce interconnect lengths and relieve routing congestion. The test chip, with 128 Kb of memory and 512 processing elements (PEs) on two fully depleted silicon-on-insulator (SOI) dies, can achieve a peak of 170 billion-bit-operations per second at 400 MHz.Index Terms-Memory architecture, multiprocessor interconnection, parallel processing, silicon-on-insulator (SOI) technology.

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“…In semiconducting electronics [33], 80 486 processors incorporated about 1 M transistors/cm with predictions of 10 M/cm by the year 2000. By 1996 semiconductor processors with 0.3 m technology at speeds of 160-433 GHz [34]- [36] were at integrations of 2.3-7.4 M/cm and integrations as high as 11 M/cm have been reported [37]. For purposes in this paper, a value of 10 M JJs/cm will be assumed.…”

Section: Josephson Junction Parametersmentioning

confidence: 99%

Future heat transfer concerns in Josephson junction computers

McFall

Chow²

1999

IEEE Trans. Comp. Packag. Technol.

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Using the superconducting properties of Josephson junctions enable extremely high switching speeds unmatched in semiconducting electronics. Much research has been conducted in recent decades in order to produce high performance electronics based on Josephson junction logic. In addition to the high speeds attainable by this technology, also of significance is the very low heat dissipated by Josephson circuits. Josephson devices have made great strides in the last ten years with microprocessors reaching levels of integration as high as 10 5 junctions/cm 2 . Dissipation in these devices is easily managed, but integrations reaching 10 7 must be considered if Josephson electronics are to compete with the complexity and functionality of semiconducting electronics. Coupling this level of integration with dissipations of 0.34 and 2.98 W/junction in low and high temperature cases respectively, produces large heat fluxes difficult to remove at cryogenic temperatures. While other technical difficulties currently overshadow heat transfer concerns, the future of Josephson electronics research will likely need to address them.

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A multimedia 32 b RISC microprocessor with 16 Mb DRAM

Cited by 44 publications

References 1 publication

Ultra-Low Power Designing for CMOS Sequential Circuits

Ultra-Low Power Designing for CMOS Sequential Circuits

Design of a 3-D fully depleted SOI computational RAM

Future heat transfer concerns in Josephson junction computers

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