A multiobjective optimization tool for Very Large Scale Integrated nonslicing floorplanning

Anand, Suchith; Saravanasankar, S.; Subbaraj, P.

doi:10.1002/cta.829

Cited by 9 publications

(5 citation statements)

References 44 publications

(64 reference statements)

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“…It was put forward by Metropolis in 1953 [34] and then applied into combinatorial optimization field by Kirkpatrick [35]. The simulated annealing algorithm has been widely used in fields such as very large scale integrated circuits, production scheduling, control engineering, machine learning, neural network, and signal processing [36]–[38]. The simulated annealing algorithm, based on iterative solution strategy, is a random optimization algorithm.…”

Section: Discussionmentioning

confidence: 99%

Using Mathematical Algorithms to Modify Glomerular Filtration Rate Estimation Equations

et al. 2013

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BackgroundThe equations provide a rapid and low-cost method of evaluating glomerular filtration rate (GFR). Previous studies indicated that the Modification of Diet in Renal Disease (MDRD), Chronic Kidney Disease-Epidemiology (CKD-EPI) and MacIsaac equations need further modification for application in Chinese population. Thus, this study was designed to modify the three equations, and compare the diagnostic accuracy of the equations modified before and after.MethodologyWith the use of 99 mTc-DTPA renal dynamic imaging as the reference GFR (rGFR), the MDRD, CKD-EPI and MacIsaac equations were modified by two mathematical algorithms: the hill-climbing and the simulated-annealing algorithms.ResultsA total of 703 Chinese subjects were recruited, with the average rGFR 77.14±25.93 ml/min. The entire modification process was based on a random sample of 80% of subjects in each GFR level as a training sample set, the rest of 20% of subjects as a validation sample set. After modification, the three equations performed significant improvement in slop, intercept, correlated coefficient, root mean square error (RMSE), total deviation index (TDI), and the proportion of estimated GFR (eGFR) within 10% and 30% deviation of rGFR (P10 and P30). Of the three modified equations, the modified CKD-EPI equation showed the best accuracy.ConclusionsMathematical algorithms could be a considerable tool to modify the GFR equations. Accuracy of all the three modified equations was significantly improved in which the modified CKD-EPI equation could be the optimal one.

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Section: Discussionmentioning

confidence: 99%

Using Mathematical Algorithms to Modify Glomerular Filtration Rate Estimation Equations

et al. 2013

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“…Sengupta et al 18 have used the technique of dynamic programming for voltage assignment to blocks for energy optimization followed by heuristic approach for partitioning of design to enable near optimal solutions for floorplanning. Anand et al 19 have proposed an optimization algorithm where a concept of archive of a set of solutions is used to improve upon the solution quality with each iteration of the annealing process.…”

Section: Introductionmentioning

confidence: 99%

Power aware floorplanning in multiple supply voltage domain

Banerjee

Roy

2021

Circuit Theory & Apps

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Floorplanning in this nano-scale era involves consideration of various other objectives apart from minimizing wirelength in a fixed outlined region. In recent era of electronic devices, reducing power consumption is an important objective which can be achieved by multiple supply voltage island aware floorplanning. Optimizing power routing resource to simplify power planning while reducing voltage drop or IR drop (represented by maximum power length) is the major goal of the proposed work. Moreover, it has been observed that locations of blocks and power pads are important considerations for IR drop optimization. The proposed work hence concentrates on generating efficient floorplan with respect to wirelength, power routing resource, and IR drop. The proposed technique uses effective heuristics along with a SAT (Boolean satisfiability)-based framework to generate efficient floorplan considering all factors. The experimental validation depicts good results with respect to power resource, wirelength, and voltage drop in a fixed outline framework.fixed outline floorplanning, multiple supply voltage, power network resource, voltage drop | INTRODUCTIONIncrease in design complexity and shrinking feature size have created newer challenges in modern floorplanning thus making floorplanning to be one of the important stages of physical design. Modern era is marked by the popularity of portable electronic devices where low power is an important design issue. SoC design now-a-days comprising of numerous blocks face the challenge of low-power design.Voltage island-driven floorplanning is a difficult instance of floorplanning scenario where modules/blocks can be assigned multiple supply voltages. Usually high voltages are assigned to blocks lying in timing critical path, and low voltages are assigned to blocks lying in non-critical paths. Thus, multiple supply voltages approach is an effective approach used in industry to reduce consumption of power thus leading to improvement of chip performance. Voltage island-driven floorplanning modules/blocks with same voltage source are generally placed together to reduce difficulty in routing of power nets. Fixed outline floorplanning has become a necessity for modern floorplanning scenario along with the objective of power management. Due to increase in circuit speed and huge decrease in feature size devices in the present era, consume greater dynamic power as well as leakage power, and dynamic power is directly proportional to supply voltage.Multivoltage designs comprise of dividing the chip into regions or areas that can operate at various voltage levels. Hence, the problem of voltage island partitioning along with fixed outline floorplanning have made modern floorplan design much more complicated. Blocks with similar voltage domains must lie in clusters so that the power network

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“…Hence, floorplanning [1][2][3][4][5][6][7] is a crucial step in VLSI circuit design [8] as it determines the quality of the deep submicron chip quality, manufacturing cost and the time-to-market. Although there are several circuit design objectives to be considered during floorplanning, such as area minimization, wirelength optimization [9], delay reduction [10,11], thermal stability [12][13][14], clock tree synthesis [15] or any combination of these objectives [16][17][18], the basic objective of floorplanning is to minimize the area of the VLSI chip.…”

Section: Introductionmentioning

confidence: 99%

Cost reduction in bottom‐up hierarchical‐based VLSI floorplanning designs

Hoo

Kanesan

Ramiah

2013

Circuit Theory & Apps

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From the industrial perspective, floorplanning is a crucial step in the VLSI physical design process as its efficiency determines the quality and the time-to-market of the product. A new perturbation method, called Cull-and-Aggregate Bottom-up Floorplanner (CABF), which consists of culling and aggregating stages, is developed to perform variable-order automated floorplanning for VLSI. CABF will generate VLSI floorplan layout by calculating the modules' dimensions' differences (hard module floorplanning problems) and the modules' areas' differences (soft module floorplanning problems). Through mathematical derivation, the hard modules floorplanning area minimization cost function (two-dimensional) during culling stage is proven that a dimensional reduction can be carried out to be the difference-based cost function (one-dimensional) which simplifies the computation. During the culling stage, CABF employs linear ordering method to select and determine the order of modules where this linear runtime complexity property allows CABF to cull the modules faster. The aggregating stage of CABF will reduce the subsequent search space of this floorplanner, and the variable order aggregation enables CABF to search for the best near-optimal solution. Based on Gigascale Systems Research Center and Microelectronics Center of North Carolina circuit benchmarks, CABF gives better optimal solutions and faster runtimes for floorplanning problems involving 9 to 600 modules. This has established that CABF is performing well in respect of reliability and scalability. Besides, CABF shows its potential to be implemented in VLSI physical design as the runtime of CABF is faster with a near-optimal outcome as compared to the other existing algorithms.

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A multiobjective optimization tool for Very Large Scale Integrated nonslicing floorplanning

Cited by 9 publications

References 44 publications

Using Mathematical Algorithms to Modify Glomerular Filtration Rate Estimation Equations

Using Mathematical Algorithms to Modify Glomerular Filtration Rate Estimation Equations

Power aware floorplanning in multiple supply voltage domain

Cost reduction in bottom‐up hierarchical‐based VLSI floorplanning designs

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