A multistep ADC family with efficient architecture

Chin, S.W.; Mayes, M.K.; Filippi, R.

doi:10.1109/isscc.1989.48214

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B Design Constraints In a Dynamic Cmos H T C H1

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“…Fig. 3 shows a dynamic CMOS latch similar to that used in [4] to amplify small differences to CMOS levels.…”

Section: B Design Constraints In a Dynamic Cmos H T C Hmentioning

confidence: 99%

Design techniques for high-speed, high-resolution comparators

Razavi

Wooley²

1992

IEEE J. Solid-State Circuits

425

121

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This paper describes precision techniques for the design of comparators used in high-performance analog-to-digita1 converters employing parallel conversion stages. Following a review of conventional offset cancellation techniques, circuit designs achieving 12-b resolution in both BiCMOS and CMOS 5-V technologies are presented. The BiCMOS comparator consists of a preamplifier followed by two regenerative stages and achieves an offset of 200 pV at a IO-MHz clock rate while dissipating 1.7 mW. In the CMOS comparator offset cancellation is used in both a single-stage preamplifier and a subsequent latch to achieve an offset of less than 300 pV at comparison rates as high as 10 MHz, with a power dissipation of 1.8 mW.

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“…Fig. 3 shows a dynamic CMOS latch similar to that used in [4] to amplify small differences to CMOS levels.…”

Section: B Design Constraints In a Dynamic Cmos H T C Hmentioning

confidence: 99%