A multistep A/D converter family with efficient architecture

Mayes, M.K.; Chin, S.W.

doi:10.1109/4.44984

Cited by 20 publications

(2 citation statements)

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“…Purely flash converters have been developed using SiGe BiCMOS [17], [18], however their bit accuracies are limited by the number of comparators needed and the enormous input capacitance generated by placing numerous transistors in parallel. The two-stage A/D converter architecture [19] is chosen for this design due to its positive tradeoffs between speed, power, and complexity. A block diagram of a two-stage converter is shown in Fig.…”

Section: A High-speed Analog-to-digital Conversionmentioning

confidence: 99%

High-Speed Reconfigurable Circuits for Multirate Systems in SiGe HBT Technology

et al. 2015

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| In this paper, we discuss the advantages and opportunities presented by high-speed (> 50 GHz) reconfigurable integrated circuits and how they may drive reconfigurable systems applications, such as software-defined radio, radar, and imaging. We propose silicon-germanium (SiGe) BiCMOS as an example technology that enables ultrafast reconfigurable systems and present several circuit designs based on SiGe heterojunction bipolar transistors (HBTs). We compare circuit designs between generations of IBM's SiGe process, including a recent 9HP process featuring devices with a cutoff frequency ðf T Þ of 300 GHz. We describe an architecture for an 8-b 80-Gs/s analog-to-digital converter (ADC) and a 48 Â 48 cell fieldprogrammable gate array (FPGA), which provide powerful solutions for useful functions, such as digital signal processing (DSP) and polyphase filtering. Other circuit concepts are described, including a voltage-controlled oscillator (VCO) with a tuning range of 26 GHz and a high-performance (80 Gb/s) crossbar switch, which provide utility in reconfigurable system applications. Measured results from fabricated implementations of these described systems are presented. We comment on future prospects of these systems and examine an emerging lateral bipolar device (f T ¼ 825 GHz) having 100Â less power consumption than conventional vertical HBTs.

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Section: A High-speed Analog-to-digital Conversionmentioning

confidence: 99%

High-Speed Reconfigurable Circuits for Multirate Systems in SiGe HBT Technology

et al. 2015

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“…Folding and/or interpolation [28] can help reduce the number of comparators required, but the architecture is still not well suited for low-power applications. Multi-step [29] ADC also require a relatively large amount of analog hardware, resulting in excessive power consumption for application in distributed sensor networks.…”

Section: Adc Architecturementioning

confidence: 99%

Low Power Current Mode ADC for CMOS Sensor IC

Agarwal

Kim

Sonkusale

2005 IEEE International Symposium on Circuits and Systems

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Low-power Current-Mode ADC for CMOS Sensor IC. (August 2005) Anuj Agarwal, B. Tech., Indian Institute of Technology, Kanpur Chair of Advisory Committee: Dr. Sameer Sonkusale A low-energy current-mode algorithmic pipelined ADC targeted for use in distributed sensor networks is presented. The individual nodes combine sensing, computation and communications into an extremely small volume. The nodes operate VITA Name:

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Effect of the method of measurement of ADC and DAC linearity on the yield of acceptable microcircuits

Vonyatytskii¹

1991

Meas Tech

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A multistep A/D converter family with efficient architecture

Cited by 20 publications

References 2 publications

High-Speed Reconfigurable Circuits for Multirate Systems in SiGe HBT Technology

High-Speed Reconfigurable Circuits for Multirate Systems in SiGe HBT Technology

Low Power Current Mode ADC for CMOS Sensor IC

Effect of the method of measurement of ADC and DAC linearity on the yield of acceptable microcircuits

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