Low Power Current Mode ADC for CMOS Sensor IC

Abstract

Low-power Current-Mode ADC for CMOS Sensor IC. (August 2005) Anuj Agarwal, B. Tech., Indian Institute of Technology, Kanpur Chair of Advisory Committee: Dr. Sameer Sonkusale A low-energy current-mode algorithmic pipelined ADC targeted for use in distributed sensor networks is presented. The individual nodes combine sensing, computation and communications into an extremely small volume. The nodes operate VITA Name:

An 8-bit, 10 kHz, 5.1 μW, 0.18 μm CMOS SAR ADC for RFID applications with sensing capabilities

“…[31] [18][35] [11] Fig. 19 The ADCs in Table 2 are ranked according to the power dissipation and sorted, from which ten best have been shown Analog Integr Circ Sig Process (2011) 66:389-405 403 fabricate micro structures in a smaller dimensions, which makes parasitic capacitive load smaller, and in this way reduces the power dissipation.…”

“…The drawback, if any, is that the ADC is based on SC circuits, which set a limit to the minimum clock frequency that can be used. Because of this, and due to the development history, the SAR ADC was still seen as a more secure way to proceed with the RFID sensor tag development [18][19][20][21][22][23].…”

An Examination of the Effect of Feature Size Scaling on Effective Power Consumption in Analog to Digital Converters

“…The reference signal is first set to half of the maximum value. If the input signal is larger than this, the MSB of the digital output (in this implementation the digital values b [1][2][3][4][5][6][7][8] ) is set and the reference value is set to three-quarters of the total. If, however, the input value is less than the reference value, then the MSB is cleared and the reference value is set to one quarter of the total.…”

“…The DAC is an eight-output current mirror with each output transistor having twice the (W/L) ratio of the previous output. The output of the DAC is controlled by a set of eight digital signals, b [1][2][3][4][5][6][7][8] I C charges or discharges the input capacitance of the inverter (based on whether it is positive or negative, respectively). This will cause the inverter chain to switch allowing a digital output an_out.…”

“…This will cause the inverter chain to switch allowing a digital output an_out. an_out is the digital feedback from the comparator used to set or clear the signals b [1][2][3][4][5][6][7][8] (as in Figure 4). In active operation, the reset signal is first set high to clear all values.…”