A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS Process

Jun, Jaehun; Song, Jaegeun; Kim, Chulwoo

doi:10.1109/tcsi.2017.2758793

Cited by 17 publications

(25 citation statements)

References 21 publications

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“…The layout structures for the larger driving cell can be designed in monolithic width, multiplier, or multi-finger as discussed in [9,12]. Monolithic width is the conventional layout design for larger size cell, while multiplier and multi-finger are the layout designs for realising the PTS structure.…”

Section: Pts Layout Optimisationmentioning

confidence: 99%

“…Work in [11] presented the low variability library with a multiplier structure at the cost of delay degradation as well. The authors of [8,12] presented the libraries with a multiplier structure due to a more compact [8] and lower energy-delay product (EDP) [12] than a multi-finger structure. However, the layout structure analysis lacks considering the other layout parameter such as standard cell height.…”

Section: Introductionmentioning

confidence: 99%

“…However, the layout structure analysis lacks considering the other layout parameter such as standard cell height. The prior works in [8,[10][11][12] developed the standard cell according to the typical commercial library height, which is 8-12track designs can be redesigned with a lower cell height for a multi-finger structure to achieve more area efficiently.…”

Section: Introductionmentioning

confidence: 99%

“…Various layout composition for INVX2 based on[12] (a) Conventional monolithic width (T8MW) structure, (b) Multiplier (T8MP) structure, (c) Multi-finger (T8MF) structure. The proposed layout composition for INVX2, (d) Layout optimised multi-finger (T8MF optimised) structure, (e) Reduced height multi-finger (T6MF) structure IET Circuits Devices Syst., 2019, Vol.…”

mentioning

confidence: 99%

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Six‐track multi‐finger standard cell library design for near‐threshold voltage operation in 130 nm complementary metal oxide semiconductor technology

Lim

Kamsani

Sidek

et al. 2019

IET Circuits, Devices & Systems

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In this study, a six-track standard cell library with a multi-finger layout structure is proposed to improve the delay, energy, and area of the digital circuit design for near-threshold operation. The proposed library is optimised by using the parasitic effects of the technology and optimising the layout. To enhance the performance and energy efficiency, inverse narrow width effect has been considered in the design, whereby the minimum width of the process was used as the based width unit. To minimise the design area, the standard cell was designed in the lowest possible height with a multi-finger layout structure. The proposed library with a few basic cells was developed and characterised in 130 nm technology, which is available for synthesis and automatic place-and-route (P&R). The proposed library was analysed and compared with two eight-track multiplier layout libraries in the cell and block design level. Based on the place-and-route results of ISCAS'85 benchmark circuits, the proposed six-track library could achieve up to 27% of delay improvement, 29% energy reduction and 44% area reduction as compared to the multiplier structure library at the minimum critical path delay.

show abstract

Section: Pts Layout Optimisationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

See 2 more Smart Citations

Six‐track multi‐finger standard cell library design for near‐threshold voltage operation in 130 nm complementary metal oxide semiconductor technology

Lim

Kamsani

Sidek

et al. 2019

IET Circuits, Devices & Systems

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show abstract

“…Recently, near threshold voltage computing (NTC) has become popular as a demand for extremely low-power applications increases [5][6][7]. Decreasing the supply voltage near or under the threshold voltage level minimizes the dynamic power of the circuits due to the quadratic dependency of VDD to power [2,3,8]. However, the reduced voltage level leads to a very large performance degradation and an exponential increase in the variations [2].…”

Section: Introductionmentioning

confidence: 99%

Channel Length Biasing for Improving Read Margin of the 8T SRAM at Near Threshold Operation

2019

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Reducing a supply voltage in order to minimize power consumption in memory is a major design consideration in this field of study. In static random access memory (SRAM), optimum energy can be achieved by reducing the voltage near the threshold voltage level for near threshold voltage computing (NTC). However, lowering the operational voltage drastically degrades the stability of SRAM. Thus, in conventional 6T SRAM, it is almost impossible to read exact data, even when a small process variation occurs. To address this problem, an 8T SRAM structure is proposed which can be widely used for improving the read stability at lower voltage operation. In this paper, we investigate the channel length biasing effect on the read access transistor of the 8T SRAM in NTC and compare this with 6T SRAM. Read stability can be improved by suppressing the leakage current due to the longer channel length. Simulation results show that, in NTC, up to a 12× read-error reduction can be achieved by the 20 nm channel length biasing in the 8T SRAM compared to 6T SRAM.

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Design and implementation of energy-efficient near-threshold standard cell library for IoT applications

Hesham

Nassar

Mostafa

2021

AEU - International Journal of Electronics and Communications

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A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS Process

Cited by 17 publications

References 21 publications

Six‐track multi‐finger standard cell library design for near‐threshold voltage operation in 130 nm complementary metal oxide semiconductor technology

Six‐track multi‐finger standard cell library design for near‐threshold voltage operation in 130 nm complementary metal oxide semiconductor technology

Channel Length Biasing for Improving Read Margin of the 8T SRAM at Near Threshold Operation

Design and implementation of energy-efficient near-threshold standard cell library for IoT applications

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