Channel Length Biasing for Improving Read Margin of the 8T SRAM at Near Threshold Operation

Abstract

Reducing a supply voltage in order to minimize power consumption in memory is a major design consideration in this field of study. In static random access memory (SRAM), optimum energy can be achieved by reducing the voltage near the threshold voltage level for near threshold voltage computing (NTC). However, lowering the operational voltage drastically degrades the stability of SRAM. Thus, in conventional 6T SRAM, it is almost impossible to read exact data, even when a small process variation occurs. To address this problem, an 8T SRAM structure is proposed which can be widely used for improving the read stability at lower voltage operation. In this paper, we investigate the channel length biasing effect on the read access transistor of the 8T SRAM in NTC and compare this with 6T SRAM. Read stability can be improved by suppressing the leakage current due to the longer channel length. Simulation results show that, in NTC, up to a 12× read-error reduction can be achieved by the 20 nm channel length biasing in the 8T SRAM compared to 6T SRAM.

Content-Addressable Memory System Using a Nanoelectromechanical Memory Switch

“…In conventional CMOS-based CAMs, a precharge circuit is used to reduce the delay, as shown in Figure 3 [4,5]. When the BL or ML voltage decreases in the precharged state during an operation, owing to the precharge circuit, the delay problem can be solved by using a sense amplifier to detect small changes [8].…”

“…Two additional transistors are used for the write operation. The upper CAM cell for the match operation uses four transistors, and the SL and BL each require three transistors for the precharge [4,5]. A total of 22 transistors was used in the CMOS-based BCAM.…”

“…Conventional random-access memory devices, such as static random-access memory (SRAM) and dynamic random-access memory (DRAM), store data during a write cycle and read a stored memory during a read cycle. As a specific memory location, called the address, must be assigned during this process, sequential memory operations are inevitable for random-access memory devices [1][2][3][4][5].…”