Content-Addressable Memory System Using a Nanoelectromechanical Memory Switch

Abstract

Content-addressable memory (CAM) performs a parallel search operation by comparing the search data with all content stored in memory during a single cycle, instead of finding the data using an address. Conventional CAM designs use a dynamic CMOS architecture for high matching speed and high density; however, such implementations require the use of system clocks, and thus, suffer from timing violations and design limitations, such as charge sharing. In this paper, we propose a static-based architecture for a low-power, high-speed binary CAM (BCAM) and ternary CAM (TCAM), using a nanoelectromechanical (NEM) memory switch for nonvolatile data storage. We designed the proposed CAM architectures on a 65 nm process node with a 1.2 V operating voltage. The results of the layout simulation show that the proposed design has up to 23% less propagation delay, three times less matching power, and 9.4 times less area than a conventional design.

A Novel Design of Low Power, Modified Pre-charge free Binary CAM Array with Pre-computation for Search-Intensive Applications

“…CAM[6] [7] [23] is constructed using transistors, it is a volatile memory, it doesn't require regular refreshing to store the data. CAM consists of basic 6T SRAM cell (2 cross coupled inverters connected back-to-back, and 2 access transistors) and separate comparison circuit (extra transistors).…”