A neocortex model implementation on reconfigurable logic with streaming memory

Vutsinas, Christopher N.; Taha, Tarek M.; Rice, Kenneth

doi:10.1109/ipdps.2008.4536533

Cited by 4 publications

(3 citation statements)

References 8 publications

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“…Other researchers have reported success in using HTMs in content-based image retrieval [16], object categorization [17], and power system security analysis [18]. Another set of researchers has explored hardware implementations and parallel architectures for HTM algorithms [19].…”

Section: Modelmentioning

confidence: 99%

“…In our research, HTMs have been used successfully in invariant pattern recognition on gray-scale images, in the identification of speakers in the auditory domain and in learning a model for motion capture data in an unsupervised manner. Other researchers have reported success in using HTMs in content-based image retrieval [16] , object categorization [17] , and power system security analysis [18] . Another set of researchers has explored hardware implementations and parallel architectures for HTM algorithms [19] .…”

Section: Modelmentioning

confidence: 99%

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Towards a Mathematical Theory of Cortical Micro-circuits

2009

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The theoretical setting of hierarchical Bayesian inference is gaining acceptance as a framework for understanding cortical computation. In this paper, we describe how Bayesian belief propagation in a spatio-temporal hierarchical model, called Hierarchical Temporal Memory (HTM), can lead to a mathematical model for cortical circuits. An HTM node is abstracted using a coincidence detector and a mixture of Markov chains. Bayesian belief propagation equations for such an HTM node define a set of functional constraints for a neuronal implementation. Anatomical data provide a contrasting set of organizational constraints. The combination of these two constraints suggests a theoretically derived interpretation for many anatomical and physiological features and predicts several others. We describe the pattern recognition capabilities of HTM networks and demonstrate the application of the derived circuits for modeling the subjective contour effect. We also discuss how the theory and the circuit can be extended to explain cortical features that are not explained by the current model and describe testable predictions that can be derived from the model.

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Section: Modelmentioning

confidence: 99%

Section: Modelmentioning

confidence: 99%

Towards a Mathematical Theory of Cortical Micro-circuits

2009

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“…The recent work by Rice et al [16], [25] and Vutsinas et al [26] explores the combined implementations in regions 3 and 4, for the GHM [13]. At this time, we are not aware of any work on custom hardware implementation of the GHM [13].…”

Section: B Existing Hardware Implementations Of Ghmmentioning

confidence: 99%

CMOL/CMOS Implementations of Bayesian Polytree Inference: Digital and Mixed-Signal Architectures and Performance/Price

Zaveri

Hammerstrom

2010

IEEE Trans. Nanotechnology

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In this paper, we focus on aspects of the hardware implementation of the Bayesian inference framework within the George and Hawkins' model. This framework is based on Judea Pearl's belief propagation. We then present a "hardware design space exploration" methodology for implementing and analyzing the (digital and mixed-signal) hardware for the Bayesian (polytree) inference framework. This, particular, methodology involves: analyzing the computational/operational cost and the related microarchitecture, exploring candidate hardware components, proposing various custom architectures using both traditional CMOS and hybrid nanotechnology CMOS/nanowire/molecular hybrid (CMOL), and investigating the baseline performance/price of these hardware architectures. The results suggest that hybrid nanotechnology is a promising candidate to implement Bayesian inference. Such implementations utilize the very high density storage/computation benefits of these new nanoscale technologies much more efficiently, for example, the throughput per 858 mm 2 obtained for CMOL-based architectures is 32-40 times better than the TPM for a CMOS based multiprocessor/multifield-programmable gate array system, and almost 2000 times better than the TPM for a single PC implementation. In general, the assessment of such hypothetical hardware architectures provides a baseline for large-scale implementations of Bayesian inference, and guidance for implementing the same using nanogrid structures.

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CMOL/CMOS Implementations of Bayesian Inference Engine: Digital and Mixed-Signal Architectures and Performance/Price – A Hardware Design Space Exploration

Hammerstrom

Zaveri

2010

CMOS Processors and Memories

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A neocortex model implementation on reconfigurable logic with streaming memory

Cited by 4 publications

References 8 publications

Towards a Mathematical Theory of Cortical Micro-circuits

Towards a Mathematical Theory of Cortical Micro-circuits

CMOL/CMOS Implementations of Bayesian Polytree Inference: Digital and Mixed-Signal Architectures and Performance/Price

CMOL/CMOS Implementations of Bayesian Inference Engine: Digital and Mixed-Signal Architectures and Performance/Price – A Hardware Design Space Exploration

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