A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design

Fang, Jia-Wei; Lin, I-Jye; Chang, Yao-Wen; Wang, Jyh-Herng

doi:10.1109/tcad.2007.891364

Cited by 66 publications

(44 citation statements)

References 10 publications

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“…2. Representative works using network-flow to solve the unordered problem include Fang et al's works on flip-chip design [6], [7], [8] and Yu et al's work on package routing [9]. Note The model in Fig.…”

Section: Unordered Escapementioning

confidence: 99%

Advances in PCB Routing

Yan

Wong

2012

IPSJ Transactions on System LSI Design Methodology

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Abstract:The increasing complexity of electronic systems has made PCB routing a difficult problem. A large amount of research effort has been dedicated to the study of this problem. In this paper, we provide an overview of recent research results on the PCB routing problem. We focus on the escape routing problem and the length-matching routing problem, which are the two most important problems in PCB routing. Other relevant works are also briefly introduced.

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Section: Unordered Escapementioning

confidence: 99%

Advances in PCB Routing

Yan

Wong

2012

IPSJ Transactions on System LSI Design Methodology

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“…If an I/O pad is not assigned to any bump pad before routing, then a router has the freedom to assign an I/O pad to bump pads during routing. Fang et al [4] first divided a peripheral-I/O flip-chip into four sectors, as illustrated in Figure 2(a). Then, for each sector, this free-assignment routing problem on a single RDL was solved by a network-flow formulation without considering U-turn routes.…”

Section: (B) Is Used To Redistribute I/o Pads To Bump Pads Without -mentioning

confidence: 99%

“…Two related works are the pad routing for area-array ICs [7] and the routing for peripheral-I/O flip-chips [4]. The work [7] first used the weighted bipartite matching algorithm to generate a netlist between bump pads and I/O pads, and then routed the nets sequentially by A*-search maze routing.…”

Section: A Previous Workmentioning

confidence: 99%

“…The sequential routing is greedy, and thus its solution quality (routability and wirelength) is often limited. Recently, Fang et al in [4] addressed the single RDL routing problem for the peripheral-I/O structure, assigned I/O pads to bump pads by dividing a flip-chip into four sectors, and applied a network-flow formulation to handle the problem for each sector. Since U-turn routes and interactions among the sectors are not considered in its approach, this networkflow formulation cannot handle the area-I/O routing problem.…”

Section: A Previous Workmentioning

confidence: 99%

“…For each tile, we can treat the routing in a tile as a channel routing. So we can extend the net-ordering determination algorithm presented in [4] to generate a routing sequence S =< (n Figure 10(a), we first redraw the boundary for all net segments except n(4, 4 ). The reason is that n(4, 4 ) must pass through the top interval.…”

Section: ) Global-routing Path Refinementmentioning

confidence: 99%

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Area-I/O flip-chip routing for chip-package co-design

Fang

Chang

2008

2008 IEEE/ACM International Conference on Computer-Aided Design

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Abstract-The area-I/O flip-chip package provides a high chip-density solution to the demand of more I/O's in VLSI designs; it can achieve smaller package size, shorter wirelength, and better signal and power integrity. In this paper, we introduce the routing problem for chip and package co-design and present the first work in the literature to handle the multiple Re-Distribution Layer (RDL) routing problem for flip-chip designs, considering pin and layer assignment, total wirelength minimization, and chip-package co-design. Our router adopts a two-stage technique of global routing followed by RDL routing. The global routing assigns each block port to a unique bump pad via an I/O pad and decides the RDL routing among I/O pads and bump pads. Based on the minimum-cost maximumflow algorithm, we can guarantee 100% RDL routing completion after the assignment and the optimal solution with the minimum wirelength. The RDL routing efficiently distributes the routing points between two adjacent bump pads and then generates a 100% routable sequence to complete the routing. Experimental results based on 10 industry designs demonstrate that our router can achieve 100% routability and the optimal routing wirelength under reasonable CPU times, while related works cannot.

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