A Neuron Library for Rapid Realization of Artificial Neural Networks on FPGA: A Case Study of Rössler Chaotic System

Koyuncu, İ̇smail; Şahin, İbrahim Fevzi; Gloster, Clay; Sarıtekin, N. K.

doi:10.1142/s0218126617500153

Cited by 22 publications

(9 citation statements)

References 13 publications

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“…Then ANN model is implemented on a digital platform by taking the weight and bias values obtained from the training as reference [28]. In ANN-based CO designs, many digital sources have been used, and since they contain non-linear transfer functions, their operating frequencies are generally low [28][29][30][31][32].…”

Section: Introductionmentioning

confidence: 99%

CCII current conveyor and dormand-prince-based chaotic oscillator designs for secure communication applications

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Pehlivan

et al. 2020

International Advanced Researches and Engineering Journal

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Chaos is one of the important research areas in recent years. The chaotic signal generator is one of the most basic structure in the chaos-based researches and applications. In this study, Sundarapandian-Pehlivan Chaotic Oscillator (SPCO) designs have been implemented in 2 different platforms as analog-based using Second-Generation Current Controlled Current Conveyor (CCII) and FPGA-based with one of the chaotic oscillator that has been presented to the literature namely Sundarapandian-Pehlivan system. The structure used for the design of CCII-based chaotic oscillator and the results obtained from the study have been presented. In the second phase, the design of SPCO has been realized in order to utilize for running in FPGA chips using Dormand-Prince (DP) numeric algorithm. The design has been coded in VHDL using 32-bit IEEE-754-1985 floating point representation. The designed system has been tested by synthesizing it in Xilinx ISE Design Tools program. Then, the test results obtained from DPbased SPCO structure have been presented. In the last phase, the designed system has been synthesized for VIRTEX-7 FPGA. FPGA chip resource consumption values that obtained after the Place-Route process are presented. According to the results, the maximum operating frequency of DP-based SPCO unit on FPGA is obtained as 362.608 MHz. In future studies, the designs of Pseudo Random Number Generator (RNG) and True RNG can be performed using DP-based SPCO unit implemented successfully in this study.

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Section: Introductionmentioning

confidence: 99%

CCII current conveyor and dormand-prince-based chaotic oscillator designs for secure communication applications

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Pehlivan

et al. 2020

International Advanced Researches and Engineering Journal

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“…According to Girau , the FPGA represents the most balanced option for the implementation of ANNs from the abovementioned technologies due to their processing speed, the semiconductor area used, the product's total cost, the design time, and implementation reliability. In fact, FPGA technology has rapidly become a computational paradigm of primary interest for research and academic communities involved in the modeling and implementation of ANNs . However, it is surprising to note that, for the most part, it is most common for undergraduate courses to use just personal computers (PCs) and software for teaching students the components and structure of ANNs.…”

Section: Introductionmentioning

confidence: 99%

A “learning by design” application for modeling, implementing, and evaluating hardware architectures for artificial neural networks at undergraduate level

Guzmán‐Ramírez

García

García-Juárez

2019

Comp Applic In Engineering

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Artificial intelligence is currently playing an important role in engineering education. Artificial neural networks (ANNs), for example, are one of the most important topics in computer science and computer engineering curricula. The teaching of ANNs, however, is challenging and current efforts are mainly focused on providing computer systems and/or software simulators to enhance results. In the present study, we introduce a field programmable gate arraybased educational system focused on the modeling, implementation, and evaluation of hardware architectures of ANNs type Multilayer Perceptron. The system was designed by taking into account the learning by design approach to creating a modular proposal, which is composed of a set of predefined modules that describe the behavior of each element of an ANN. This feature allows various neural architectures to be easily defined and to be applied to different specific problems. The system helps the teaching-learning process by providing a design environment where undergraduate students can apply the knowledge acquired in lecture-based courses related to areas, such as pattern recognition and neural networks. The experimental results present the design and implementation of an ANN hardware architecture that solves the iris-plant problem. K E Y W O R D Sartificial intelligence, artificial neural networks, engineering education, FPGA

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“…Chaotic oscillators are expressed by using differential equations and these equations can be modeled with different numerical algorithms. Euler [25], Heun [26], the fourth order Runge Kutta (RK4) [27], and fifth order Runge Kutta Butcher (RK5-Butcher) [28] can be given as an example.…”

Section: Introductionmentioning

confidence: 99%

Implementation of Dormand-Prince based chaotic oscillator designs in different IQ-Math number standards on FPGA

Koyuncu

Şeker

2019

Sakarya University Journal of Science

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Chaos and chaotic systems, one of the most important work areas in recent years, are used in areas such as cryptology and secure communication, industrial control, artificial neural networks, random number generators and image processing. The most basic structure used in these studies is a chaotic oscillator design that produces a chaotic signal. Chaotic oscillators are expressed by using differential equations. Numerical algorithms such as Euler, Heun, fourth order Runge-Kutta-4 (RK4), fifth order RK5-Butcher and Dormand-Prince are used for solving these differential equations. When the current literature is searched, chaotic oscillator designs are found by Euler, Heun, RK4 and RK5-Butcher method. However, FPGA-based chaotic oscillator design studies have not been found using the Dormand-Prince method, which produces more accurate solutions than other methods. In this work, self-excited attractor chaotic system was first designed in 16I-16Q, 14I-14Q, 12I-12Q, 10I_10Q, 8I-8Q IQ-Math number standards on FPGA using Dormand-Prince numerical algorithm and encoded in VHDL language. Xilinx ISE Design Tools were used to design the chaotic system. The design was synthesized and tested for the Xilinx Virtex-6 FPGA chip. Using the Xilinx ISE design tool, the chip statistics and maximum operating frequency obtained after the "Route-Place" operation are presented. In future work, safe communication and real random number generator applications can be realized by using the Dormand-Prince based oscillator design presented in this study.

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A Neuron Library for Rapid Realization of Artificial Neural Networks on FPGA: A Case Study of Rössler Chaotic System

Cited by 22 publications

References 13 publications

CCII current conveyor and dormand-prince-based chaotic oscillator designs for secure communication applications

CCII current conveyor and dormand-prince-based chaotic oscillator designs for secure communication applications

A “learning by design” application for modeling, implementing, and evaluating hardware architectures for artificial neural networks at undergraduate level

Implementation of Dormand-Prince based chaotic oscillator designs in different IQ-Math number standards on FPGA

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