A new 65nm LP metastability measurment test circuit

Beer, Salomon; Ginosar, Ran

doi:10.1109/eeei.2012.6377044

Cited by 4 publications

(3 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The tapped chain of logic functions, 20 the tapped inverter chain, 12 and apparently also the \delay line" mentioned by Beer et al 21 are very close in nature to our proposed approach. As will be outlined in more detail in the next subsection, we propose the use of a carry chain instead.…”

Section: Control Of the Resolution Timesupporting

confidence: 67%

“…Circuit-level simulators, such as SPICE, have been successfully employed to observe the metastable behavior of an element. [10][11][12] While they allow convenient access without probing e®ects, they use idealized models that may not appropriately re°ect the actual circuit parameters, and they tend to su®er from numerical problems and high sensitivity to even small changes in the chosen parameters and models. 13 Consequently, by far the most popular method for assessing metastability characteristics is based on the following observation:…”

Section: Basic Options For Metastability Measurementmentioning

confidence: 99%

See 1 more Smart Citation

An Experimental Study of Metastability-Induced Glitching Behavior

Polzer

Huemer

Steininger

2019

J CIRCUIT SYST COMP

View full text Add to dashboard Cite

The increasing number of clock domain crossings in modern systems-on-chip makes the careful consideration of metastability paramount. However, the manifestation of metastability at a flip-flop output is often unduly reduced to late transitions only, while glitches are hardly ever accounted for. In this paper we study the occurrence of glitches resulting from metastability in detail. To this end we propose a measurement circuit whose principle substantially differs from the conventional approach, and by that allows to reliably detect glitches. By means of experimental measurements on an FPGA target we can clearly identify late transitions, single glitches and double glitches as possible manifestations of metastability. Some of these behaviors are unexpected as they do not follow from the traditional modeling theory. We also study the dependence of metastable behavior on supply voltage. Beyond confirming that, as reported in previous literature, the metastable decay constant [Formula: see text] is voltage-dependent, we also produce strong evidence that the relative occurrence of glitches is not voltage-dependent.

show abstract

Section: Control Of the Resolution Timesupporting

confidence: 67%

Section: Basic Options For Metastability Measurementmentioning

confidence: 99%

An Experimental Study of Metastability-Induced Glitching Behavior

Polzer

Huemer

Steininger

2019

J CIRCUIT SYST COMP

View full text Add to dashboard Cite

show abstract

“…A detailed study on the metastability behavior The metastability in shape of undefined output voltage can be converted into a late transition and so analog modeling is not required [11]. A more efficient modeling approach that is also tractable for large circuits is proposed based on modeling the dependence of the output delay on the temporal displacement between the data transition and the disabling of the latch.…”

Section: Synchronizer Performance Is Based On Mtbf (Mean Time Between Failures) Three Experimentsmentioning

confidence: 99%

Analysis of Metastability for the Synchronizer of NoC

Jiang¹,

Kim²

2014

The Journal of the Korea institute of electronic communication

View full text Add to dashboard Cite

Bus architecture of SoC has been replaced by NoC in recent years. Noc uses the multi-clock domains to transmit and receive data between neighbor network interfaces and they have same frequency, but a phase difference because of clock skew. So a synchronizer is used for a mesochronous frequency in interconnection between network interfaces. In this paper the metastability is defined and analyzed in a D latch and a D flip-flop to search the possibilities that data can be lost in the process of sending and receiving data between interconnects when a local frequency and a transmitted frequency have a phase difference. 180nm CMOS model parameter and 1GHz are used to simulate them in HSpice. The simulation results show that the metastability happens in a latch and a flip-flop when input data change near the clock edges and there are intermediate states for a longer time as input data change closer at the clock edge. And the next stage can lose input data depending on environmental conditions such as temperature, processing variations, power supply, etc. The simulation results are very useful to design a mescochronous synchronizer for NoC

show abstract