A new algorithm for energy-driven data compression in VLIW embedded processors

Abstract

This paper presents a new algorithm for on-the-fly data compression in high performance VLIW processors. The algorithm aggressively targets energy minimization of some of the dominant factors in the SoC energy budget (i.e., main memory access and high throughput global bus). Based on a differential technique, both the new algorithm and the HW compression unit have been developed to efficiently manage data compression and decompression into a high performance industrial processor architecture, under strict real time constraints (Lx-ST200: A 4-issue, 6-stages pipelined VLIW processor with on-chip D and I-Cache). The original Data-Cache line is compressed before write-back to main memory and, then, decompressed whenever Cache refill takes place. An extensive experimental strategy has been developed for the specific validation of the target Lx processor. In order to allow public comparison, we also report the results obtained on a MIPS pipelined RISC processor simulated with SimpleScalar. The two platforms have been benchmarked over Ptolemy and MediaBench programs. Energy savings provided by the application of the proposed technique range from 10% to 22% on the Lx-ST200 platform and from 11% to 14% on the MIPS platform.

Increasing on-chip memory space utilization for embedded chip multiprocessors through data compression

“…While such specialized architectures generate very good results from both power and performance angles, the resulting design may not be very flexible as the data access pattern of the entire application should be captured in a single memory configuration. Data compression has also been used to reduce memory footprint and energy consumption in the past [1,2,10,21,22]. In [4] data compression is used to reduce the energy consumption in DRAMs by increasing the effectiveness of low-power operating modes.…”

Harnessing horizontal parallelism and vertical instruction packing of programs to improve system overall efficiency

“…Moreover, they lack the ability to physically pack instructions to reduce the hardware cost, program code size, and energy consumption in memory. In [11], the authors managed to reduce the program code size and the memory access energy cost in VLIW architectures by applying instruction compression/decompression between memory and cache. However, it also requires complex compression algorithms and hardware implementation, and the power consumption of the processor has not been effectively reduced.…”

On-Chip Memory Management for Embedded MpSoC Architectures Based on Data Compression

“…It is to be noted that addressing this problem is particularly important for embedded MpSoCs as these systems are primarily targeted at embedded environments that process large amounts of data. Data compression has been one of the ways of reducing memory footprint and energy consumption in the past [8,4]. Consequently, one could expect that it could so be used in an MpSoC-based environment.If used correctly, data compression can improve the execution cycles and reduce memory power consumption as it reduces the amount of data that needs to be accessed from the memory and needs to be communicated over the bus (i.e., by storing more data in the on-chip memory, we reduce the volume and frequency of off-chip memory activity).…”