A New Approach for Screening Retention Time Failure Bits in DRAM Device

Abstract

In this paper, we investigate that Gate-Induced Drain Leakage (GIDL)-weak cells can be screened effectively by modulation of cell-plate voltage (VPlate) during retention time in dynamic random access memory (DRAM) with Negative Wordline bias scheme (NWL). Boosting storage-node voltage (VSP) by increase of VPlate is the root cause of generating additional GIDL fail bits.