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In this paper, we investigate that Gate-Induced Drain Leakage (GIDL)-weak cells can be screened effectively by modulation of cell-plate voltage (VPlate) during retention time in dynamic random access memory (DRAM) with Negative Wordline bias scheme (NWL). Boosting storage-node voltage (VSP) by increase of VPlate is the root cause of generating additional GIDL fail bits.

Body effect is the key characteristic of DRAM cell transistor. Conventional method uses a TEG structure for body effect measurement. But this measurement is not accurate, because TEG structure has only several transistors and it is located outside of the DRAM die. This paper suggests a viable method for measuring DRAM cell transistor body effect. It uses a memory test system for fast, massive, nondestructive measurement. Newly developed method can measure 100,000 DRAM cell body effects in two minute, without sample damage. The test gives one median value and 100,000 individual values of body effects. Median value of measured body effects is equal to the TEG body effect. An individual DRAM cell body effect has a correlation with the fin height.

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