A new approach to constructing optimal parallel prefix circuits with small depth

Lin, Yen–Chun; Hsiao, Jun-Wei

doi:10.1016/j.jpdc.2003.09.004

Cited by 18 publications

(20 citation statements)

References 22 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Because computation speed is the essential factor in applications that need prefix computations with massive data, prefix computation circuits, which are suitable for hardware implementation, have also been proposed in the literature [9,10,21,22,36]. Approaches for building parallel prefix circuits found in the literature mainly focus on reducing the depth of the circuit, by using bypass edges, to minimize the total execution time.…”

Section: Algorithm 1: Parallel Prefix Summentioning

confidence: 99%

“…There exist a number of depth reduction schemes used in prefix computation circuits in the literature [10,21,22,36], but they are not applicable to our design since they do not accord with the motivations of our design in exploiting scalability, reconfigurability, and modularity. For example with the simple full tree reduction scheme shown in Fig.…”

Section: Depth Reductionmentioning

confidence: 99%

See 1 more Smart Citation

Reconfigurable hardware solution to parallel prefix computation

Park

Dai

2007

J Supercomput

View full text Add to dashboard Cite

This paper presents the design and implementation of an efficient reconfigurable parallel prefix computation hardware on field-programmable gate arrays (FPGAs). The design is based on a pipelined dataflow algorithm, and control logic is added to reconfigure the system for arbitrary parallelism degree. The system receives multiple input streams of elements in parallel and produces output streams in parallel. It has an advantage of controlling the degree of parallelism explicitly at run time. The time complexity of the design is O(d + (N − d)/d), where d and N are parallelism degree and stream size, respectively. When the stream size is sufficiently larger than the initial trigger time of the pipeline (d), the time complexity becomes O(N/d). Unlike the prefix computation circuits found in the literature, the design is scalable for different problem sizes including unknown sized data. The design is modular based on a finite state machine, and implemented and tested for target FPGA devices Xilinx Spartan2S XC2S300EFT256-6Q and XC2S600EFG676-6.

show abstract

Section: Algorithm 1: Parallel Prefix Summentioning

confidence: 99%

Section: Depth Reductionmentioning

confidence: 99%

Reconfigurable hardware solution to parallel prefix computation

Park

Dai

2007

J Supercomput

View full text Add to dashboard Cite

show abstract

“…Lin and others have done a lot of work in this respect, that is, constructing zero-deficiency 1 prefix circuits of limited fan-out, especially 2 and 4 [Lin 1999;Lin and Chen 2003;Lin and Hsiao 2004]. Their approaches are largely constructive and cannot be generalized for arbitrary fan-out constraints.…”

Section: Zero-deficiency Prefix Circuits Of Limited Fan-outmentioning

confidence: 99%

On the construction of zero-deficiency parallel prefix circuits with minimum depth

Zhu

Cheng

Graham

2006

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

A parallel prefix circuit has n inputs x 1 , x 2 , . . . , x n , and computes the n outputs y i = x i • x i−1 • · · · • x 1 , 1 ≤ i ≤ n, in parallel, where • is an arbitrary binary associative operator. Snir proved that the depth t and size s of any parallel prefix circuit satisfy the inequality t + s ≥ 2n− 2. Hence, a parallel prefix circuit is said to be of zero-deficiency if equality holds. In this article, we provide a different proof for Snir's theorem by capturing the structural information of zero-deficiency prefix circuits. Following our proof, we propose a new kind of zero-deficiency prefix circuit Z (d ) by constructing a prefix circuit as wide as possible for a given depth d . It is proved that the Z (d ) circuit has the minimal depth among all possible zero-deficiency prefix circuits.

show abstract

“…, x n , and for a binary associative operation *, the prefix computation of the sequence is defined as outputs y i , 1 ≤ i ≤ n, y i = x 1 * x 2 * · · · * x i . Numbers of parallel prefix combinational structures have been proposed over the past years [4][5][6][7][8][9][10][11][12][13][14][15]. These combinational circuits intend to optimize area and speed through having circuits of minimum depth and/or size [16,17] (the depth of a circuit is the number of levels in the circuit, while the size is the number of operation nodes in the circuit).…”

mentioning

confidence: 99%

“…Most of the recent depth-size optimal prefix circuits are constructed using waist-size optimal with waist 1 (WSO-1) circuits as building blocks [6,7,10] (a waist-size optimal prefix circuit, A, is a circuit that has the property size(A)+waist(A) = 2m − 2 [17]). Thus, it is useful to have optimal circuits of any width to support construction of depth-size optimal prefix circuits of any larger width [17].…”

mentioning

confidence: 99%

Dynamic-width reconfigurable parallel prefix circuits

El-Boghdadi

2015

J Supercomput

View full text Add to dashboard Cite

Parallel prefix circuits have drawn high interest because of their importance in many applications such as fast adders. Most proposed parallel prefix circuits assume fixed width. The input size could be of the same width as the circuit or different than the width of the circuit. In this paper, we propose a class of reconfigurable parallel prefix circuits,Ř-circuits, that support different operational modes. TheŘ-circuit can be reconfigured as one parallel prefix circuit of high width as well as several smaller width parallel prefix circuits that can operate on different prefix problems in parallel. In particular, anŘ-circuit,Ř(k(m)), of width km with k building blocks (slices) each of width m, can be configured as a number of z prefix circuits, z ≤ k, each of width b j , such that z j=1 b j = km. For a circuit C R b ∈Ř(k(m)) of b slices and width bm, we show how such circuit can be constructed. We derive a bound for the depth of C R b and show how C R b can handle input size n ≥ bm. Then, we show the performance ofŘ(k(m)) and compare it with other fixed same-width prefix circuits.

show abstract

A new approach to constructing optimal parallel prefix circuits with small depth

Cited by 18 publications

References 22 publications

Reconfigurable hardware solution to parallel prefix computation

Reconfigurable hardware solution to parallel prefix computation

On the construction of zero-deficiency parallel prefix circuits with minimum depth

Dynamic-width reconfigurable parallel prefix circuits

Contact Info

Product

Resources

About