On the construction of zero-deficiency parallel prefix circuits with minimum depth

Abstract

A parallel prefix circuit has n inputs x 1 , x 2 , . . . , x n , and computes the n outputs y i = x i • x i−1 • · · · • x 1 , 1 ≤ i ≤ n, in parallel, where • is an arbitrary binary associative operator. Snir proved that the depth t and size s of any parallel prefix circuit satisfy the inequality t + s ≥ 2n− 2. Hence, a parallel prefix circuit is said to be of zero-deficiency if equality holds. In this article, we provide a different proof for Snir's theorem by capturing the structural information of zero-deficiency prefix circuits. Following our proof, we propose a new kind of zero-deficiency prefix circuit Z (d ) by constructing a prefix circuit as wide as possible for a given depth d . It is proved that the Z (d ) circuit has the minimal depth among all possible zero-deficiency prefix circuits.

Improved Area-Efficient Weighted Modulo $2^{n} + 1$ Adder Design With Simple Correction Schemes

“…Before presenting the delay/area synthesis results, the delay/area comparisons for the translation stage in terms of n are given in Table II, which demonstrates our area savings over the work in [17]. We adopt Sklansky-style [12], [19], [20] and Brent-Kungstyle [21] parallel-prefix structures for the diminished-1 adder implementations. The diminished-1 adder based on the Sklansky-style parallel-prefix structure with correction circuits for our proposed weighted modulo 2 8 + 1 adder is shown in Fig.…”

Reconfigurable hardware solution to parallel prefix computation

“…Because computation speed is the essential factor in applications that need prefix computations with massive data, prefix computation circuits, which are suitable for hardware implementation, have also been proposed in the literature [9,10,21,22,36]. Approaches for building parallel prefix circuits found in the literature mainly focus on reducing the depth of the circuit, by using bypass edges, to minimize the total execution time.…”

“…There exist a number of depth reduction schemes used in prefix computation circuits in the literature [10,21,22,36], but they are not applicable to our design since they do not accord with the motivations of our design in exploiting scalability, reconfigurability, and modularity. For example with the simple full tree reduction scheme shown in Fig.…”

Dynamic-width reconfigurable parallel prefix circuits

“…, x n , and for a binary associative operation *, the prefix computation of the sequence is defined as outputs y i , 1 ≤ i ≤ n, y i = x 1 * x 2 * · · · * x i . Numbers of parallel prefix combinational structures have been proposed over the past years [4][5][6][7][8][9][10][11][12][13][14][15]. These combinational circuits intend to optimize area and speed through having circuits of minimum depth and/or size [16,17] (the depth of a circuit is the number of levels in the circuit, while the size is the number of operation nodes in the circuit).…”

“…Most of the recent depth-size optimal prefix circuits are constructed using waist-size optimal with waist 1 (WSO-1) circuits as building blocks [6,7,10] (a waist-size optimal prefix circuit, A, is a circuit that has the property size(A)+waist(A) = 2m − 2 [17]). Thus, it is useful to have optimal circuits of any width to support construction of depth-size optimal prefix circuits of any larger width [17].…”