In this brief, we proposed improved area-efficient weighted modulo 2 n + 1 adders. This is achieved by modifying existing diminished-1 modulo 2 n + 1 adders to incorporate simple correction schemes. Our proposed adders can produce modulo sums within the range {0, 2 n }, which is more than the range {0, 2 n − 1} produced by existing diminished-1 modulo 2 n + 1 adders. We have implemented the proposed adders using 0.13-µm CMOS technology, and the area required for our adders is lesser than previously reported weighted modulo 2 n + 1 adders with the same delay constraints.Index Terms-Modulo 2 n + 1 adder, residue number system (RNS), VLSI design.

In a recent paper by Lin and Sheu, the authors have proposed a new circular-carry-selection technique that is applied in the design of an efficient diminished-one modulo 2 n + 1 adder. The proposed modulo adder in the aforementioned paper consists of a dual-sum carry look-ahead (DS-CLA) adder, a circular carry generator, and a multiplexer, which can reduce both area-time (AT) and time-power (TP) products compared with previous modulo adders. However, in our investigation, there will be incorrect results on the calculation of modulo addition because the carry-in of the DS-CLA adder is equal to zero. To remedy this drawback, we propose the corrected architecture of the DS-CLA adder based on the equations proposed in the aforementioned paper, which can perform correct modulo addition. The complexity of the corrected architecture is almost the same as the one proposed by Lin and Sheu but with less area cost, which can also have the same merits of both AT and TP products.Index Terms-Circular carry selection (CCS), modulo 2 n + 1 adder, residue number system (RNS), VLSI design.Suppose the two n-bit diminished-one operands are denoted by A

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