This brief presents a logic synthesis flow that depends on the popular Synopsys Design Compiler to perform logic translation and minimization based on the standard cell library with both pass transistor logic (PTL) and CMOS logic cells. The hybrid PTL/CMOS logic synthesis can generate appropriate circuits considering various design constraints. The proposed multilevel PTL logic cells are automatically constructed from only a few basic cells. Postlayout simulations with UMC 90-nm technology are presented based on the standard cell library with pure PTL, pure CMOS, or hybrid PTL/CMOS cells. Experimental results show that, in most cases, pure PTL circuits have smaller area and power, whereas CMOS circuits, in general, have smaller delay. Index Terms-Cell-based design, LEAn Pas-transistor (LEAP), logic synthesis, pass transistor logic (PTL), standard cell library.
Thalassemia was first described by Cooley and Lee in 1952 in several Italian children as a severe anemia with spleen and liver enlargement, skin discoloration, and bony changes. Great strides in management and intervention have not been matched by progress in psychosocial rehabilitation. Because parental stress and adaptation are of concern, this study focuses on parental stress and adjustment in response to the disease process of their afflicted children in western Taiwan. The parents of 18 thalassemia major patients (under 12 years of age) were interviewed (in two sessions) to determine their feelings, sources of stress, and support during their childrens' disease process. The study found that: 1) many parents suffer from stress as a result of the disease process, 2) all parents had similar concerns about iron chelation treatment, and 3) some resilience factors were present in the support system.
Exclusive-OR (XOR) gate is one of the critical components in many applications such as cryptography. In this paper, we present an efficient multi-input XOR circuit design based on pass-transistor logic (PTL). A synthesis algorithm is developed to efficiently generate the PTL-based multi-input XOR circuits. Both pre-layout and post-layout simulation results show that our proposed multi-input XOR design outperforms static CMOS design. The multi-input XOR circuits are also used to design the transformations in the Advanced Encryption Standard (AES).
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