Para-CORDIC: Parallel CORDIC Rotation Algorithm

An Optimization of CORDIC Algorithm and FPGA Implementation

“…Since all of these operations are on the critical path of the each iteration, the time of iteration and consumption of area are greatly increased. Angle encoder CORDIC algorithm could greatly reduce the number of iterations at the cost of increasing the latency of a single iteration, and skip some unnecessary rotation angle so that the scaling factor is no longer a constant [6].…”

CORDIC Architectures: A Survey

“…The rotation by θ H are performed as in the conventional CORDIC algorithm and the iterations related to θ L can be 14 VLSI Design simplified as in linear coordinate system. This algorithm led to the development of several parallel CORDIC algorithms [63][64][65]. These can be categorized broadly as mixed-hybrid CORDIC and partitioned-hybrid CORDIC algorithms.…”

“…The implementation is designed to keep the fast timing characteristics of redundant arithmetic in the x/ y path of the CORDIC processing. In the partitioned-hybrid CORDIC [63,64], the first n/3 direction of rotations are generated using the first n/3 bits of θ and last 2n/3 direction of rotations are predicted using the 2n/3 least significant bits of θ.…”

“…The scale factor compensation is implemented using a multiplier designed with CS adder tree. [64]. The Para-CORDIC parallelizes the generation of direction of rotations σ from the binary value of the input angle θ by employing binary to bipolar representation (BBR) and microrotation angle recoding (MAR) techniques.…”

“…In [64], Para-CORDIC algorithm is proposed to precompute the direction of rotations without using ROM, while eliminating iterative z path completely. This method uses additional x/ y stages for the repetition of a certain microrotations to predict the direction of rotations in contrast to ROM employed in [61,63,65].…”