Corrections to “VLSI Design of Diminished-One Modulo $2^{n} + 1$ Adder Using Circular Carry Selection” [Sep 08 897-901]

Abstract

In a recent paper by Lin and Sheu, the authors have proposed a new circular-carry-selection technique that is applied in the design of an efficient diminished-one modulo 2 n + 1 adder. The proposed modulo adder in the aforementioned paper consists of a dual-sum carry look-ahead (DS-CLA) adder, a circular carry generator, and a multiplexer, which can reduce both area-time (AT) and time-power (TP) products compared with previous modulo adders. However, in our investigation, there will be incorrect results on the calculation of modulo addition because the carry-in of the DS-CLA adder is equal to zero. To remedy this drawback, we propose the corrected architecture of the DS-CLA adder based on the equations proposed in the aforementioned paper, which can perform correct modulo addition. The complexity of the corrected architecture is almost the same as the one proposed by Lin and Sheu but with less area cost, which can also have the same merits of both AT and TP products.Index Terms-Circular carry selection (CCS), modulo 2 n + 1 adder, residue number system (RNS), VLSI design.Suppose the two n-bit diminished-one operands are denoted by A

Improved Area-Efficient Weighted Modulo $2^{n} + 1$ Adder Design With Simple Correction Schemes

“…There are many previously reported methods to speed up the modulo 2 n + 1 addition. Depending on the input/output data representations, these methods can be classified into two categories, namely, diminished-1 [11]- [16] and weighted [17], [18], respectively.…”

“…In [13] and [14], the authors proposed efficient parallel-prefix adders for diminished-1 modulo 2 n + 1 addition. To improve the area-time and time-power products, the circular carry selection scheme was used to efficiently select the correct carry-in signals for final modulo addition [15], [16]. The aforementioned methods all deal with diminished-1 modulo addition.…”

“…In addition, the value zero is not allowed in diminished-1 modulo 2 n + 1 addition, and hence, the zero-detection circuit is required to avoid incorrect computation. This leads to increased hardware cost, which was not considered in the designs proposed in [13]- [16].…”