A new approach to designing electronic systems for operation in extreme environments: Part II - The SiGe remote electronics unit

England, Troy; Diestelhorst, R.M.; Kenyon, Eleazar W.; Cressler, John D.; Ramachandran, V.; Alles, M.; Reed, Robert A.; Berger, Richard W.; Garbos, R.; Blalock, Benjamin J.; Mantooth, Alan; Barlow, M.; Dai, Fa Foster; Johnson, Wayne; Ellis, Charles D.; Holmes, Jim; Webber, C.; McCluskey, Patrick; Mojarradi, Mohammad; Peltz, Leora; Frampton, Robert; Eckert, Charles A.

doi:10.1109/maes.2012.6328839

Cited by 21 publications

(6 citation statements)

References 15 publications

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“…110 A few attempts have been made to interface quantum devices with cryogenic electronics to reduce the wiring toward room temperature, 26-28, 105, 111, 112 but those approaches have been limited to one or two quantum devices, thus not truly addressing the scalability issues of quantum computers. However, by relying on the progress of semiconductor technology, only CMOS technology can currently offer the integration of billions of transistors on a single chip, while ensuring low-power consumption, reliability, and functionality down to 30 mK.…”

Section: Scalable Classical Cmos Control Electronics For Fault-toleramentioning

confidence: 99%

“…by reducing the thermal noise in readout for high-energy or nuclear physics experiments [93], or to serve in harsh environments, e.g. in space applications [94,95]. A few attempts have been made to interface quantum devices with cryogenic electronics to reduce the wiring towards room temperature [23,24,26,[96][97][98], but those approaches have been limited to one or two quantum devices, thus not truly addressing the scalability issues of quantum computers.…”

Section: Scalable Classical Cmos Control Electronics For Fault-tolera...mentioning

confidence: 99%

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Quantum information density scaling and qubit operation time constraints of CMOS silicon-based quantum computer architectures

et al. 2017

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Even the quantum simulation of an apparently simple molecule such as Fe 2 S 2 requires a considerable number of qubits of the order of 10 6 , while more complex molecules such as alanine (C 3 H 7 NO 2 ) require about a hundred times more. In order to assess such a multimillion scale of identical qubits and control lines, the silicon platform seems to be one of the most indicated routes as it naturally provides, together with qubit functionalities, the capability of nanometric, serial, and industrial-quality fabrication. The scaling trend of microelectronic devices predicting that computing power would double every 2 years, known as Moore's law, according to the new slope set after the 32-nm node of 2009, suggests that the technology roadmap will achieve the 3-nm manufacturability limit proposed by Kelly around 2020. Today, circuital quantum information processing architectures are predicted to take advantage from the scalability ensured by silicon technology. However, the maximum amount of quantum information per unit surface that can be stored in silicon-based qubits and the consequent space constraints on qubit operations have never been addressed so far. This represents one of the key parameters toward the implementation of quantum error correction for faulttolerant quantum information processing and its dependence on the features of the technology node. The maximum quantum information per unit surface virtually storable and controllable in the compact exchange-only silicon double quantum dot qubit architecture is expressed as a function of the complementary metal-oxide-semiconductor technology node, so the size scale optimizing both physical qubit operation time and quantum error correction requirements is assessed by reviewing the physical and technological constraints. According to the requirements imposed by the quantum error correction method and the constraints given by the typical strength of the exchange coupling, we determine the workable operation frequency range of a silicon complementary metal-oxide-semiconductor quantum processor to be within 1 and 100 GHz. Such constraint limits the feasibility of fault-tolerant quantum information processing with complementary metal-oxide-semiconductor technology only to the most advanced nodes. The compatibility with classical complementary metal-oxide-semiconductor control circuitry is discussed, focusing on the cryogenic complementary metal-oxide-semiconductor operation required to bring the classical controller as close as possible to the quantum processor and to enable interfacing thousands of qubits on the same chip via timedivision, frequency-division, and space-division multiplexing. The operation time range prospected for cryogenic control electronics is found to be compatible with the operation time expected for qubits. By combining the forecast of the development of scaled technology nodes with operation time and classical circuitry constraints, we derive a maximum quantum information density for logical qubits of 2.8 and 4 Mqb/cm 2 for the 10 and 7-...

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Section: Scalable Classical Cmos Control Electronics For Fault-toleramentioning

confidence: 99%

Section: Scalable Classical Cmos Control Electronics For Fault-tolera...mentioning

confidence: 99%

Quantum information density scaling and qubit operation time constraints of CMOS silicon-based quantum computer architectures

et al. 2017

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“…Previous work on circuits for total ionizing dose (TID) effects have been systemically conducted for the last forty years, although it has predominantly focused on the outer space field because of the many projects organized by NASA [ 3 , 4 ]. This research for space applications has been mainly investigated for degradation of single transistor performances such as threshold voltage shift, leakage current increase, trans-conductance reduction, and electrical noise increase caused by radiation [ 5 , 6 , 7 , 8 , 9 , 10 ].…”

Section: Introductionmentioning

confidence: 99%

Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad

Lee

Cho

Unruh

et al. 2020

Sensors

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According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad around a reactor in-core required. In harsh radiating environments such as NPPs, sensors such as micro-pocket-fission detectors (MPFD) would be a promising technology to be operated for detecting neutrons in reactor cores. For those sensors, readout circuits should be fundamentally placed close to sensing devices for minimizing signal interferences and white noise. Therefore, radiation hardening ability is necessary for the circuits under high radiation environments. This paper presents various integrated circuit designs for a radiation hardened charge-sensitive amplifier (CSA) by using SiGe 130 nm and Si 180 nm fabrication processes with different channel widths and transistor types of complementary metal-oxide-semiconductor (CMOS) and bipolar CMOS (BiCMOS). These circuits were tested under γ–ray environment with Cobalt-60 of high level activity: 490 kCi. The experiment results indicate amplitude degradation of 2.85%–34.3%, fall time increase of 201–1730 ns, as well as a signal-to-noise ratio (SNR) of 0.07–11.6 dB decrease with irradiation dose increase. These results can provide design guidelines for radiation hardening operational amplifiers in terms of transistor sizes and structures.

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“…Silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) have received extensive attention for implementation in extreme-environment applications due to their excellent total-ionizing-dose (TID) tolerance, high-speed operation (i.e., high unity gain frequency, f T ), superb cryogenic performance, and ease of integration in a complementary metal oxide semiconductor (CMOS) platform [1][2][3][4]. However, studies have reported that SiGe HBTs are susceptible to single-event phenomena, especially single-event upset (SEU) and single-event transient (SET) [5][6][7], and thus, it is highly critical that the sensitivity of SiGe HBT circuits to single-event effect (SEE) be improved, either via changing the underlying device profile, i.e., radiation hardening by process (RHBP) or circuit Sensors 2020, 20, 2581 2 of design, i.e., radiation hardening by design (RHBD), or both. Developing radiation-hardened platforms require significant effort to optimize and are very expensive.…”

Section: Introductionmentioning

confidence: 99%

Mitigation of Single-Event Effects in SiGe-HBT Current-Mode Logic Circuits

Sarker

Jung

Ildefonso

et al. 2020

Sensors

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It has been known that negative feedback loops (internal and external) in a SiGe heterojunction bipolar transistors (HBT) DC current mirrors improve single-event transient (SET) response; both the peak transient current and the settling time significantly decrease. In the present work, we demonstrate how radiation hardening by design (RHBD) techniques utilized in DC bias blocks only (current mirrors) can also improve the SET response in AC signal paths of switching circuits (e.g., current-mode logic, CML) without any additional hardening in those AC signal paths. Four CML circuits both with and without RHBD current mirrors were fabricated in 130 nm SiGe HBT technology. Two existing RHBD techniques were employed separately in the current mirrors of the CML circuits: (1) applying internal negative feedback and (2) adding a large capacitor in a sensitive node. In addition, these methods are also combined to analyze the overall SET performance. The single-event transients of the fabricated circuits were captured under the two-photon-absorption laser-induced single-event environment. The measurement data clearly show significant improvements in SET response in the AC signal paths of the CML circuits by using the two radiation hardening techniques applied only in DC current mirrors. The peak output transient current is notably reduced, and the settling time upon a laser strike is shortened significantly.

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A new approach to designing electronic systems for operation in extreme environments: Part II - The SiGe remote electronics unit

Cited by 21 publications

References 15 publications

Quantum information density scaling and qubit operation time constraints of CMOS silicon-based quantum computer architectures

Quantum information density scaling and qubit operation time constraints of CMOS silicon-based quantum computer architectures

Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad

Mitigation of Single-Event Effects in SiGe-HBT Current-Mode Logic Circuits

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