A new approach to FET model scaling and MMIC design based on electromagnetic analysis

Cidronali, Alessandro; Collodi, Giovanni; Vannini, G.; Santarelli, Alberto

doi:10.1109/22.769324

Cited by 36 publications

(22 citation statements)

References 28 publications

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“…1, where, for simplicity and without loss of generality, a two-finger device has been considered. In particular, the model consists of a "passive distributed network" to which "active slices" are interconnected [20]. The passive structure is characterized by means of its scattering matrix , which is computed by using electromagnetic simulation on the basis of layout geometry and material parameters.…”

Section: Empirical Distributed Modelmentioning

confidence: 99%

mentioning

confidence: 99%

“…They are based on the common idea of an extrinsic passive network feeding a cascade of elementary active devices [20]- [28]. In comparison with other approaches, the empirical model presented in [20] adopts a distributed description both for the active device area and extrinsic structure. In particular, according to this FET modeling approach, the active area is partitioned into a convenient number of "internal elementary devices" (or "active slices") fed by a "passive distributed structure."…”

mentioning

confidence: 99%

“…Although these models are potentially accurate, they are still in a preliminary phase and their application to practical problems such as circuit analysis, design, and optimization may be difficult, also taking into account their computational cost [7]- [12]. On the other hand, there is an increasing demand for comprehensive and effective analysis/design tools able to consider simultaneously (i.e., "global modeling" [13]- [20]) all the interacting circuit elements, active and passive devices, radiation elements, and packaging influence.…”

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confidence: 99%

“…In [20], the empirical distributed model was adopted in order to predict, as a function of the device periphery and number of gate fingers, small-signal -parameters (up to 50 GHz) for GaAs MESFETs. In particular, preliminary experimental results have confirmed the consistency of the model pointing out useful robust scaling properties, which enable transistor geometric parameters to be considered as circuit design variables.…”

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confidence: 99%

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Millimeter-wave FET modeling using on-wafer measurements and EM simulation

Cidronali

Collodi

Santarelli

et al. 2002

IEEE Trans. Microwave Theory Techn.

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Abstract-Electron device modeling is a challenging task at millimeter-wave frequencies. In particular, conventional approaches based on lumped equivalent circuits become inappropriate to describe complex distributed and coupling effects, which may strongly affect the transistor performance. In this paper, an empirical distributed FET model is adopted that can be identified on the basis of conventional -parameter measurements and electromagnetic simulations of the device layout. The consistency of the proposed approach is confirmed by robust scaling properties, which enable millimeter-wave small-signal -parameters to be predicted as a function of the device periphery and number of gate fingers. Moreover, it is shown how the model identified on the basis of standard -parameter measurements up to 50 GHz can be efficiently exploited in order to obtain reasonably accurate small-signal prediction up to 110 GHz. Extensive experimental validation is presented for 0.2-m pseudomorphic high electron-mobility transistors devices.

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Section: Empirical Distributed Modelmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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Millimeter-wave FET modeling using on-wafer measurements and EM simulation

Cidronali

Collodi

Santarelli

et al. 2002

IEEE Trans. Microwave Theory Techn.

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Optimization‐based approach for scalable small‐signal and noise model extraction of GaN‐on‐SiC HEMTs

Colangeli

Ciccognani

Cleriti

et al. 2015

Int J Numerical Modelling

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SUMMARYAn optimization-based method allowing a straightforward extraction of scalable small-signal equivalent-circuit models for high-frequency active devices is proposed. The approach only requires a set of devices with a fixed number of fingers and scaling unit gate widths: no dummy structures or bias conditions potentially harmful for the devices are needed. The extraction method is then demonstrated by presenting in full a sample extraction, carried out on a 0.25 GaN-on-SiC HEMT technology provided by Selex-ES. The example also includes the extraction of a noise model, by means of a well-known noise-temperature approach. Both the small-signal and noise models agree well with the experimental data.

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Direct extraction method of HEMT switch small‐signal model with multiparasitic capacitive current path

Yuan

Yang

et al. 2018

Int J RF Microw Comput Aided Eng

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It has been found that the analytical extraction methods cannot be applied to the usual test structure of the switch high electron-mobility transistor (HEMT) with a large-value gate grounded resistor. The significant effect of the precise multicapacitive current path on switch model precision has also been found. The multicapacitive current path here is different from the seemingly similar hypothesis proposed for the distributed parasitic effects at high frequencies (eg, D-band). In fact, for switch based HEMT, it is important to distinguish between the capacitive current paths accurately even at relatively low frequencies. Due to the existing of the large gate resistance, the usual capacitance mix decreases the accuracy of the switch model significantly. Thus an analytical method has been developed to calculate parasitic capacitances (the capacitance to ground and the interelectrode capacitance) through full-wave electromagnetic analysis. For practical applications and further verification, the whole HEMT switch small-signal models and the direct extraction methods are presented. The simulated results fit well with the measurements up to 40 GHz. K E Y W O R D S electromagnetic analysis, high electron-mobility transistor, interelectrode parasitic capacitance, microwave switches, small-signal model 1 | INTRODUCTION In 1988, Dambrine et al.proposed an analytical way to extract FET small-signal equivalent circuit parameters. 1 All the parasitic parameters were analytically extracted by using cold-FET method. After de-embedding all the parasitic effects from the whole S parameters, the intrinsic parameters were calculated by analytical equations. 2 De-embedding methods, cold-FET techniques, and analytical equations 3 are used by lots of FET small-signal model extraction methods today. Note that Reference 1 also has some limitations, for example, the pinch-off intrinsic model used to determine the parasitic capacitance parameters tends to overestimate the value of the drain to ground capacitance (C pd ). The high positive gate bias condition used to determine the parasitic inductances and resistances have the potential to destroy the gate Schottky diode. 4 In addition, for high electron-mobility transistors (HEMTs), it is difficult to apply enough high gate bias to ignore the gate capacitance effect. 5,6 Many works are making improvements to meet the needs of new semiconductor technologies and new applications like high frequency applications. 7-11 The small-signal modeling is also the basis of the large-signal and noise modeling. [12][13][14] As stated above, lots of articles and effort has been dedicated to common-source FET small-signal modeling, but high-frequency switch FET small-signal modeling is still difficult. Very few works concern switch FET small-signal modeling. [15][16][17][18][19][20][21] Numerical solutions concern intrinsic effects only and are difficult to meet measured behavior. [15][16][17] The simplified equivalent circuits cannot capture full feature of the switch HEMT at high frequencies. 18,19...

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A new approach to FET model scaling and MMIC design based on electromagnetic analysis

Cited by 36 publications

References 28 publications

Millimeter-wave FET modeling using on-wafer measurements and EM simulation

Millimeter-wave FET modeling using on-wafer measurements and EM simulation

Optimization‐based approach for scalable small‐signal and noise model extraction of GaN‐on‐SiC HEMTs

Direct extraction method of HEMT switch small‐signal model with multiparasitic capacitive current path

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