A New Approach to Hierarchical and Statistical Timing Simulations

Benkoski, J.; Strojwas, Andrzej J.

doi:10.1109/tcad.1987.1270345

Cited by 35 publications

(7 citation statements)

References 28 publications

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“…One reason for greater cost is the need for repeating the simulation with different delay values (since worst case delays may not be the maximum values). Some approaches mitigate the problem by reusing results in repeated fixed delay simulations [4], using ambiguity delay simulation [14,8], or a combination of fixed delay simulation and path tracing [5].…”

Section: A Classificationmentioning

confidence: 99%

Automated multi-cycle symbolic timing verification of microprocessor-based designs

Gupta

Siewiorek

1994

Proceedings of the 31st Annual Conference on Design Automation Conference - DAC '94

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Timing verification ascertains whether timing checks on components in a circuit are satisfied given component delay models. This paper addresses timing verification of microprocessor-based designs for which previous approaches are shown to be inadequate. It introduces the concept of sequential path tracing -tracing paths through both space and time -that forms the basis of the mtv tool. mtv has the following novel features: unlike previous approaches, it considers sequential behavior together with timing and handles sequential sensitizability and multi-cycle paths automatically; it does not require a predefined clock schedule and can handle circuits with conditional or gated clocks, multiple unrelated clocks, asynchronous set/reset, and power-up initialization; it generates symbolic constraints between timing attributes of components that can be efficiently re-used for small circuit changes or by a synthesis/optimization tool; symbolic constraints also enable common ambiguity removal.Experimental results demonstrate that mtv takes only a few CPU minutes to generate symbolic constraints for each of several microprocessor-based designs.

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Section: A Classificationmentioning

confidence: 99%

Automated multi-cycle symbolic timing verification of microprocessor-based designs

Gupta

Siewiorek

1994

Proceedings of the 31st Annual Conference on Design Automation Conference - DAC '94

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“…:, (Su et a/. 1986) and to design a unified model for hierarchical timing simulation (Benkoski andStrojwas 1987, Lin andMead 1986).…”

Section: Arij -Sv(yt -~ " ) ( X ( W ) I -X ( W ) J ) ~+ S " ( X ; -Xmentioning

confidence: 99%

“…468 C.-J. Shi 1983, timing simulators (Benkoski andStrojwas 1987, Chu andHorowitz 1987), circuit extraction programs (Su el a/. 1986), macromodelling (Brocco el a/.…”

Section: Introductionmentioning

confidence: 99%

Analysis, sensitivity and macromodelling of the Elmore delay in linear networks for performance-driven VLSI design

Shi

1993

International Journal of Electronics

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“…[7,81). Their strategy consists in pre-characterizing cells a t high hierarchical levels as accurately as possible, thus obtaining relatively accurate results a t reduced computational costs.…”

Section: Introductionmentioning

confidence: 99%

A new accurate and hierarchical timing analysis approach

Blaquiere¹,

Dagenais²,

Savaria³

1993 European Conference on Design Automation With the European Event in ASIC Design

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A n~w and cficicnt procedure is proposed to evaluate the timing performance of VLSI circuits with rzrcuit level accuracy. The efficiency is obtained by rapidly identifying the crilical portions of the circuit al high hierarchical levels with rough delay modcls. These portions are then successively studied at i7ior-e detailed lcvels for inaxzinal accuracy. This procedure, itiipleinented and applied to several circuits, is shown to stgnificanily reduce the analysis time.

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A New Approach to Hierarchical and Statistical Timing Simulations

Cited by 35 publications

References 28 publications

Automated multi-cycle symbolic timing verification of microprocessor-based designs

Automated multi-cycle symbolic timing verification of microprocessor-based designs

Analysis, sensitivity and macromodelling of the Elmore delay in linear networks for performance-driven VLSI design

A new accurate and hierarchical timing analysis approach

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