A new architecture for FPGA implementation of a MAC unit for digital signal processors using mixed number system

Ghosh, Aniruddha; Singha, Satrughna; Sinha, Amitabha

doi:10.1145/2234336.2234342

Cited by 5 publications

(4 citation statements)

References 8 publications

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“…Main objective of a conventional MAC unit is multiplication and accumulation. The term accumulation signifies its ability of performing addition operation and accumulate the sum of the previous consecutive products [17]. So, multiplier, adder and accumulator are required for implementing MAC unit.…”

Section: Architecture Of Mac Unit Using Tnsmentioning

confidence: 99%

“…and 'M' is the trit length of product. For implementing this architecture [21], TNS Adder, Barrel Shifter [17] and LUT are required. TNS Adder is used to add the indices.…”

Section: Dbtns Multiplier Unitmentioning

confidence: 99%

“…Multiplication and accumulation operation can be performed in single cycle by MAC unit. In the architecture of the proposed MAC unit[2][12][17], there are two input h(n) and x(n) which is in TNS. Initially, they are converted into DBTNS.…”

mentioning

confidence: 99%

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FPGA Implementation of MAC Unit for Double Base Ternary Number System (DBTNS) and its Performance Analysis

Ghosh¹,

Sinha²

2018

IJCA

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New methodologies for efficiently describing and implementing digital systems are investigated as the complexity of binary digital hardware system is relentlessly expanding. From the recent study, it is shown that multi valued logic approach is more advantageous over existing binary digital system. Ternary means a multilevel switching component, which switches between 3 levels. Recent study on ternary number system (TNS), has shown numerous advantages over binary. In recent times, Double Base Number Systems (DBNS) are considered as alternatives to binary number system because of their capabilities of performing partial product free multiplications. On the other hand, Double Base Ternary Number System (DBTNS) multipliers are efficient compared to conventional TNS multiplier. High performance digital signal processing systems which can able to handle all Digital Signal Processing (DSP) algorithms, broadly utilize Multiply-Accumulate (MAC) operation. So, TNS Adder and DBTNS Multipliers can be used to implement fast MAC units. Keeping this in view, a new approach of designing efficient MAC unit using DBTNS multiplier is proposed in this work. The performance of proposed MAC unit is compared with conventional ternary multiplier-based MAC unit and they are mapped on a FPGA chip. Performance analysis clearly indicates that the supremacy of the proposed architecture over conventional ternary multiplier-based MAC unit.

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Section: Architecture Of Mac Unit Using Tnsmentioning

confidence: 99%

“…and 'M' is the trit length of product. For implementing this architecture [21], TNS Adder, Barrel Shifter [17] and LUT are required. TNS Adder is used to add the indices.…”

Section: Dbtns Multiplier Unitmentioning

confidence: 99%

See 1 more Smart Citation

FPGA Implementation of MAC Unit for Double Base Ternary Number System (DBTNS) and its Performance Analysis

Ghosh¹,

Sinha²

2018

IJCA

Self Cite

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“…LUT) based[23]. In DBTNS, there are two bases, one is 2 and another is 3 and the number is represented in terms of power 2 and 3 i.e i j X=2 .3 where these indices (i, j) are in ternary number system[19][28]. Here, the values of i and j are stored in different location of LUT as shown in figure 3.…”

mentioning

confidence: 99%

Performance Analysis of FPGA Based MAC Unit using DBTNS Multiplier & TRNS Adder for Signal Processing Algorithm

Ghosh

Sinha²

2018

AIVP

Self Cite

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Digital signal processing (DSP) algorithms are actually nothing but sum of product. So, they are computationally intensive. All the mathematical tasks related to DSP algorithm are based on multiplication and addition. So, the implementations of DSP algorithms-based applications extensively require multiplier and adder. Due to extensive use of multiplication and addition operation, speed up cannot be achieved. Designing the high-performance adder and multiplier are primary objective for implementing high performance signal processing applications. This hindrance can be removed by Multiply-Accumulate Unit (MAC). The special feature of a MAC unit is its ability to perform single cycle multiplication and addition operation. The performance of MAC Unit can be improved by using non-binary number system. Ternary value logic (TVL) has the ability to offer several advantages over conventional binary number system like reduce chip area, reduce overall delay. TVL can switch between three levels, such levels denoted by 0, 1, 2. As Residue Number Systems (RNS) can perform "carry free" arithmetic operations, high performance adder can be implemented using RNS in TVL domain (TRNS). Partial product free multiplication can be implemented by using Double Base Number System in TVL domain (DBTNS). Double Base Ternary Number System (DBTNS) multiplier can perform better than conventional TVL multiplier. A MAC unit is used to perform the multiplication and accumulator operations together to avoid unnecessary overhead on the processor in terms of processing time and the on-chip memory requirements. Keeping in view of these issues, a new architecture is proposed for implementing high performance MAC unit for DSP applications. In this paper, a new approach of designing MAC unit is instigated using DBTNS multiplier and TRNS adder. A major bottleneck of implementing this architecture is the complexity involved in converting TVL to DBTNS in initial stage and converting TRNS to TVL in final stage. The performance of Ternary Residue Number Systems (TRNS) system depends on selection of moduli because selection of moduli is not properly maintained then it will affect system speed, dynamic range and hardware complexity. Proposed MAC unit is mapped on field programmable gate array (FPGA) for analysis its performance.

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Comparative Analysis for Conversion of Double Base Number System (DBNS) from Conventional Number System Using Binary Search Algorithm by Changing Base Patterns for ANN-Based Applications

Singha,

Ghosh

2024

Lecture Notes in Networks and Systems

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A new architecture for FPGA implementation of a MAC unit for digital signal processors using mixed number system

Cited by 5 publications

References 8 publications

FPGA Implementation of MAC Unit for Double Base Ternary Number System (DBTNS) and its Performance Analysis

FPGA Implementation of MAC Unit for Double Base Ternary Number System (DBTNS) and its Performance Analysis

Performance Analysis of FPGA Based MAC Unit using DBTNS Multiplier & TRNS Adder for Signal Processing Algorithm

Comparative Analysis for Conversion of Double Base Number System (DBNS) from Conventional Number System Using Binary Search Algorithm by Changing Base Patterns for ANN-Based Applications

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