New methodologies for efficiently describing and implementing digital systems are investigated as the complexity of binary digital hardware system is relentlessly expanding. From the recent study, it is shown that multi valued logic approach is more advantageous over existing binary digital system. Ternary means a multilevel switching component, which switches between 3 levels. Recent study on ternary number system (TNS), has shown numerous advantages over binary. In recent times, Double Base Number Systems (DBNS) are considered as alternatives to binary number system because of their capabilities of performing partial product free multiplications. On the other hand, Double Base Ternary Number System (DBTNS) multipliers are efficient compared to conventional TNS multiplier. High performance digital signal processing systems which can able to handle all Digital Signal Processing (DSP) algorithms, broadly utilize Multiply-Accumulate (MAC) operation. So, TNS Adder and DBTNS Multipliers can be used to implement fast MAC units. Keeping this in view, a new approach of designing efficient MAC unit using DBTNS multiplier is proposed in this work. The performance of proposed MAC unit is compared with conventional ternary multiplier-based MAC unit and they are mapped on a FPGA chip. Performance analysis clearly indicates that the supremacy of the proposed architecture over conventional ternary multiplier-based MAC unit.
Execution of arithmetic operations at very high speed in real time is the major concern in digital signal processing (DSP) because DSP algorithms are computation intensive. In recent times, Residue Number Systems (RNS) are considered as alternative to binary number system because of their capabilities of performing "carry-free" addition and Multiplication. Double Base Number Systems (DBNS), another non-binary number systems are also increasingly becoming attractive for signal processing applications due to their capabilities of handling arithmetic operations, particularly multiplication efficiently. However, the complexity involved in converting binary to DBNS becomes a major bottleneck and the efficiency of performance decreases considerably due to large conversion time. So RNS Adder and DBNS Multiplier can be used to implement multiply & accumulate (MAC) units. Because RNS adders are less complex and faster compared to DBNS and DBNS multipliers are efficient compared to RNS multiplier. MAC units are the key units in Digital Signal Processors. In this paper we have shown how FIR filter can be implemented using the proposed "Mixed Number System MAC units".
Compute intensive signal Processing Algorithms demand efficient execution of high performance arithmetic operations. Since, double base number system (DBNS) offers high performance arithmetic units, it is gaining attention to many researchers .However, the advantage of DBNS can not be exploited due to large conversion time from binary to DBNS. Keeping this issue in view, this paper presents a novel conversion scheme using parallel search technique.
Novel high speed energy efficient square root architecture has been reported in this paper. In this architecture, we have blended ancient Indian Vedic mathematics and Bakhshali mathematics to achieve a significant amount of accuracy in performing the square root operation. Basically, Vedic Duplex method and iterative division method reported in Bakhshali Manuscript have been utilized for that computation. The proposed technique has been compared with the well known Newton-Raphson's (N-R) technique for square root computation. The algorithm has been implemented and tested using Modelsim simulator, and performance parameters such as the number of lookup tables, propagation delay and power consumption have been estimated using Xilinx ISE simulator. The functionality of the circuitry has been checked using Xilinx Virtex-5 FPGA board.
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